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fk suffix (pb-free) 98asa00428d 23 pin pqfn (12 x12 mm) 06XS4200 ordering information device temperature range (t a ) package mc06XS4200fk - 40 to 125 c 23 pqfn high side switch document number: mc06XS4200 rev. 1.0, 8/2012 freescale semiconductor ? advance information ? freescale semiconductor, in c., 2012. all rights reserved. *this document contains certain info rmation on a product under development. ? freescale reserves the right to change or discontinue this product without notice dual 24 v, 6.0 mohm high side switch the 06XS4200 device is part of a 24 v dual high side switch product fa mily with integrated control and a high number of protective and diagnostic functions. it has been designed for truck, bus, and industrial applications. the low r ds(on) channels (<6.0 m? ) ca n control different load types; bulbs, solenoids, or dc motors. control, device configuration, and diagnostics are performed through a 16-bit serial peripheral interface (spi), allowing easy integration into existing applications. both channels can be controlled individually by external/internal clock-sign als or by direct inputs. using the internal clock allows fully autonomous device operation. progr ammable output voltage slew rates (individually programmable) help improve emc performance. to avoid shutting off the device during in rush current, while still being able to closely track the load current, a dynamic over-current threshold profile is featured. switching curr ent of each channel can be sensed with a programmable sensing ratio. whenever communication with the external microcontroller is lost, t he device enters a fail-safe operation mode, but remains operational, controllable, and protected. features ? two fully-protected 6.0 m ? (@ 25 c) high side switches ?up to 9.0 a steady-state current per channel ? separate bulb and dc motor latched over-current handling ? parallel output operating m ode with improved switching synchronization ? individually programmable internal/external pwm clock signals (switching frequency, duty cycle, sl ew rate, switch -on time-shift) ? over-current, short-circuit, and ov er-te mperature protection with programmable auto-retry functions ? accurate temperature and current sensing (high/low sensing ratios/off set compensation) ? open-load detection (channel in off and on state), also for led app lications (7.0 ma typ.) ? normal operating range: 8.0 - 36 v, extended range: 6.0 - 58 v, 3.3 v and 5.0 v compatible 16-bit spi po rt for device control, configuration, and diagnosti cs at rates up to 8.0 mhz mcu v dd clock fsb sclk csb so rstb si in0 in1 csns gnd vdd vpwr hs0 hs1 load i/o sclk csb si i/o so i/o i/o a/d gnd load m conf0 conf1 fsob i/o a/d sync i/o 06XS4200 v dd v pwr figure 1. simplified application diagram
analog integrated circuit device data ? 2 freescale semiconductor 06XS4200 internal block diagram internal block diagram gnd over-temperature detect. control severe short-circuit selectable over-current internal regulator selectable slew rate gate driver over/under-voltage protections hs0 vpwr vdd csb sclk so si rstb clock fsb in0 hs1 hs0 hs1 in1 detection output csns i dwn i up open-load detect detection temperature feedback v reg short-circuit to charge v dd failure detection calibratable oscillator * pwm module drain/gate clamp r dwn current sense analog mux over-temperature prewarning pump por fsob conf0 conf1 i up v reg i dwn sync i dwn vpwr detec. logic * *blocks marked in grey have been implemented independently for each of both channels figure 2. internal block diagram
analog integrated circuit device data freescale semiconductor 3 06XS4200 table of contents table of contents internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pin assignment and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 functional internal block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 functional device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 operation and operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 logic commands and spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
analog integrated circuit device data ? 4 freescale semiconductor 06XS4200 pin connections pin connections transparent top view 1 12 10 9 8 7 6 5 4 3 2 20 19 15 14 13 hs0 hs1 csns in1 fsob conf0 conf1 fsb rstb csb sclk si vdd gnd vpwr 11 23 22 21 16 17 18 clock in0 sync gnd vpwr so gnd vpwr 06XS4200 figure 3. device pin assignments table 1. 06XS4200 pin assignments the function of each pin is described in the section functional description pin number pin name function formal name definition 1 csns output output current/ temper ature monitoring this pin either outputs a current proportional to the channel?s output current or a voltage pr oportional to the temperature of the gnd pin (pin 14). selection between current and temperature sensing, as well as setting the current sensing sensitivity are performed through the spi interface. an external pull- down resistor must be connected between csns and gnd. 2 3 in0 in1 input direct inputs the in[0 : 1] input pins are used to directly control the switching state of both switches a nd consequently the voltage on the hs0 : hs1 output pins. the pins are connected to gnd b y internal pull-down resistors 4 fsob output fail-safe output ( active low) fsob is asserted (active-low) upon entering fail-safe mode (see functional description ) this open-drain output requires an external pull-up resistor to v pwr 5 6 conf0 conf1 input configuration input the conf[0 : 1] input pins are used to select the appropriate over-current detect ion profile (bulb/dc motor) for each of both channels. conf requires a pull-down resistor to gnd. 7 fsb output fault status ( active low) this open-drain output pin (external pull-up resistor to v dd required) is set when the device enters fault mode (see fault mode ) 8 clock input pwm clock the clock input gives the time-base wh en the device is operated in external clock/internal pwm mode. this pin has an internal pull-down current source. 9 rstb input reset this input pin is used to initialize the dev ice?s configuration - and fault registers. reset will put the device in sleep mode (l ow current consumption) provided it is not stimulated by direct input signals.this pin is connected to gnd by an internal pull-down resistor. 10 csb input chip select ( active low) this input pin is connected to the spi chip-select output of an external - controller. csb is internally pulled up to v dd by a current source i up .
analog integrated circuit device data freescale semiconductor 5 06XS4200 pin connections 11 sclk input serial clock this input pin is to be connected to an external spi clock signal. the sclk pin is internally connected to a pull-down current source i dwn 12 si input serial input this input pin receives the spi i nput data from an external device (microcontroller or another extreme swit ch device in case of daisy-chaining). the si pin is internally connected to a pull-down current source i dwn 13 vdd power digital drain voltage this is the positive supply pin of the spi interface. 16 so output serial output this output pin transmits spi dat a to an external device (external microcontroller or the si pin of the nex t spi device in case of daisy-chaining). the pin doesn?t require external pull-up or pull-down resistors, but a series resistor is recommended to limit curr ent consumption in case of gnd disconnection 14, 17, 22 gnd ground ground these pins, internally connected, are th e ground pins for the logic - and analog circuitry. it is recommended to al so connect these pins on the pcb. 15,18,21 vpwr power positive power supply these pins, internally connected, s upply both the device?s power and control circuitry (except the spi port). the drain of both internal mosfet switches is connected to them. pin 15 is the device?s primary thermal pad. 19 20 hs1 hs0 output power switch outputs output pins of the switches, to be connected to the load. 23 sync output output current monitoring synchronization this output pin is asserted (active lo w) when the current sense (cs) output signal is within the specif ied accuracy range. readi ng the sync pin allows the external microprocessor to synchroni ze to the device when operating in autonomous operating mode. sync is open-drain and requires a pull-up resistor to v dd . table 1. 06XS4200 pin assignments (continued) the function of each pin is described in the section functional description pin number pin name function formal name definition
analog integrated circuit device data 6 freescale semiconductor 06XS4200 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are relative to ground unless mentioned othe rwise. exceeding these ratings may cause permanent damage. parameter symbol maximum ratings unit electrical ratings vpwr supply voltage range load dump at 25 c (500 ms) reverse battery at 25 c (2 min.) fast negative transient pulses (iso 7637-2 pulse #1, v pwr =14v & ri=10 : ) v pwr 58 -28 -60 v vdd supply voltage range v dd -0.3 to 5.5 v voltage on input pins (1) (except in[0:1]) and output pins (2) (except hs[0:1]) v max,logic (1) -0.3 to 5.5 v voltage on fail-safe output (fsob) v fso -0.3 to 58 v voltage on so pin v so -0.3 to v dd +0.3 v voltage (continuous, max. allowable) on in[0:1] inputs v in,max 58 v voltage (continuous, max. allowable) on output pins (hs [0:1]), v hs[0:1] -28 to 58 v rated continuous output current per channel (3) i hs[0:1] 9.0 a maximum allowable energy dissipation per channel and two parallel channels, single-pulse method (4) e cl [0:1]_sing 480 mj maximum allowable energy dissipation per channel and two parallel channels, repetitive-pulses condition. 1 (5) e cl [0:1]_rep1 > 350 mj maximum allowable energy dissipation per channel and two parallel channels, repetitive-pulses condition. 2 (6) e cl [0:1]_rep2 > 350 mj esd voltage (7) human body model (hbm) for hs[0:1], vpwr and gnd human body model (hbm) for other pins charge device model (cdm) package corner pins (1, 13, 19, 20) all other pins v esd1 v esd2 v esd3 v esd4 8000 2000 750 500 v notes: 1. concerned input pins are: conf[0:1], rstb, si, sclk, clock, and csb. 2. concerned output pins are: csns, sync, and fsb. 3. output current rating valid as long as ma ximum junction temperature is not exceeded. for computation of the maximum allowable output current, the thermal resistance of the package & th e underlying heatsink must be taken into account 4. single pulse energy dissipation, single-pulse short-circuit method (l l = 2.0 mh, r = 30 m : v pwr = 28 v, t j = 150 q c initial). 5. dissipation during repetitive cycl es: switch off upon short-circuit (l l = 20 h, r = 200 m : v pwr = 28 v, t j = 125 q c initial, f s <2.0 hz). 6. dissipation during repetitive cycle s: switch off upon short-circuit (l l = 40 h, r = 400 m : v pwr = 28 v, t j = 125 q c initial, f s <2.0 hz). 7. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 : ), and the charge device model (cdm), robotic (c zap = 4.0 pf).
analog integrated circuit device data freescale semiconductor 7 06XS4200 electrical ch aracteristics maximum ratings thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 q c storage temperature t stg - 55 to 150 q c thermal resistance / junction to case r t jc <1.0 q c/ w reflow peak temperature on device pins during soldering (8) , (9) t solder 260 q c notes: 8. 10 seconds maximum duration. not designed for immersion solder ing. exceeding these limits may cause malfunction or permanent damage to the device. msl level will be specified later. 9. freescale?s package reflow capability meets pb-free requir ements for jedec standard j-std-020. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.fr eescale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings (continued) all voltages are relative to ground unless mentioned othe rwise. exceeding these ratings may cause permanent damage. parameter symbol maximum ratings unit
analog integrated circuit device data 8 freescale semiconductor 06XS4200 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit supply electrical characteristics supply voltage range: full specification compliant extended mode (10) v pwr 8.0 6.0 24 ? 36 58 v v pwr supply current, device in wake-up mode, channel on, open-load outputs in on-state, hs[0 : 1] open, in[0:1] > v ih i pwr(on) ? 6.5 8.0 ma v pw r supply current, device in wake-up mode (standby), channel off open-load in off-state detection disabled, hs[0 : 1] shorted to ground with v dd = 5.5 v and rstb > v wake i pwr(sby) ? 6.5 8.0 ma sleep state supply current v pwr = 24 v, rstb = in[0:1] < v wake , hs[0 : 1] connected to ground t a = 25 c t a = 125 c i pwr(sleep) ? ? 3.0 ? 10.0 60.0 p a v dd supply voltage v dd(on) 3.0 ? 5.5 v v dd supply current at v dd = 5.5 v no spi communication 8.0 mhz spi communication (11) i dd(on) ? ? ? 5.0 2.2 ? ma v dd sleep state current at v dd = 5.5 v with or without v pwr i dd(sleep) ? ? 5.0 p a over-voltage shutdown threshold v pwr(ov) 39 42 45.5 v over-voltage shutdown hysteresis v pwr(ovhys) 0.2 0.8 1.5 v under-voltage shutdown threshold (12) v pwr(uv) 5.0 ? 6.0 v v pwr power-on-reset (por) voltage threshold (12) v pwr(por) 2.2 2.6 4.0 v v dd power-on-reset (por) voltage threshold (12) v dd(por) 1.5 2.0 2.5 v v dd supply failure voltage threshold (assumed v pwr > v pwr(uv) ) v dd(fail) 2.2 2.5 2.8 v notes 10. in extended mode, availability of several device functions (channel control, value of r ds(on) , over-temperature protection) is guaranteed, but compliance with the specified values in this document is not. below 6.0 v, the device is only protected from overheating (thermal shutdown). above v pwr(ov) , the channels can only be turned on when the ov er-voltage detection f unction has been disabled. 11. typical value guaranteed per design. 12. when the device recovers from under-voltage and returns to normal mode (6.0 v < v pwr < 58 v) before the end of the auto-retry period (see auto-retry ), the device will perform normally. when v pwr drops below v pwr(uv) , under-voltage is detected (see under-voltage fault (latchable fault) and emc performances ).
analog integrated circuit device data 9 freescale semiconductor 06XS4200 electrical characteristics static electrical characteristics electrical characteristics of the output stage (hs0 and hs1) on-resistance, drain-to-source (i hs = 3.0 a, t j = 25 c) csns_ratio = 0 v pwr = 8.0 v v pwr = 28 v v pwr = 36 v r ds(on)25_0 ? ? ? ? ? ? 6.0 6.0 6.0 m : on-resistance, drain-to-source (i hs = 1.0 a, t j = 25 c) csns_ratio = 1 v pwr = 8.0 v v pwr = 28 v v pwr = 36 v r ds(on)25_1 ? ? ? ? ? ? 6.0 6.0 6.0 m : on-resistance, drain-to-source (i hs = 3.0 a,t j = 150 c) csns_ratio = 0 v pwr = 8.0 v v pwr = 28 v v pwr = 36 v r ds(on)150_0 ? ? ? ? ? ? 12 12 12 m : on-resistance, drain-to-source (i hs = 1.0 a,t j = 150 c) csns_ratio = 1 v pwr = 8.0 v v pwr = 28 v v pwr = 36 v r ds(on)150_1 ? ? ? ? ? ? 12 12 12 m : on-resistance, drain-to-source difference from one channel to the other in parallel mode (i hs = 1.0 a,t j = 150 c) csns_ratio = x ' r ds(on)150 -0.7 ? +0.7 m : on-resistance, source-drain (i hs = -3.0 a, t j = 150 c, v pwr = -24 v) r sd(on)150 ? ? 12 m : max. detectable wiring length (2.5 mm2) for severe short-circuit detection (see severe short-circuit fault (latchable fault) ): high slew rate selected medium slew rate selected: low slew rate selected: l short 14 30 60 48 100 200 80 170 340 cm over-current detection thres holds with csns_ratio bit = 0 (csr0) i _och1_0 i _och2_0 i _ocm1_0 i _ocm2_0 i _ocl1_0 i _ocl2_0 i _ocl3_0 90.0 58.3 36.1 22.2 15.0 10.0 5.0 110.0 70.0 43.3 26.7 18.0 12.0 6.0 128.3 81.7 50.6 31.1 21.0 14.0 7.0 a over-current detection thres holds with csns_ratio bit = 1(csr1) i _och1_1 i _och2_1 i _ocm1_1 i _ocm2_1 i _ocl1_1 i _ocl2_1 i _ocl3_1 30.6 19.4 12.0 7.4 5.0 3.3 1.6 36.7 23.3 14.4 8.9 6.0 4.0 2.0 42.8 27.2 16.9 10.4 7.0 4.7 2.4 a table 3. static electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 06XS4200 electrical characteristics static electrical characteristics output (hs[x]) leakage current in sleep state (positive value = outgoing) v hs,off = 0 v (v hs,off = output voltage in off state) v hs,off = v pwr , device in sleep state (v pwr = 24 v max.) i out_leak ? -40.0 ? ? +16 +5.0 a switch turn-on threshold for supply over-voltage (v pwr -gnd) v d_gnd(clamp) 58 ? 66 v switch turn-on threshold for dr ain-source over-voltage (@ i hs = 100 ma) v ds(clamp) 58 ? 66 v switch turn-on threshold for drain- source over-voltage difference from one channel to the other in parallel mode (@ i hs = 100 ma) ' v ds(clamp) -2.0 ? +2.0 v current sensing ratio (13) csns_ratio bit = 0 (high-current mode) csns_ratio bit = 1 (low-current mode) c sr0 c sr1 ? ? 1/5000 1/1666.6 ? ? ? minimum measurable load current with compensated error (14) < 35% i _load_min ? ? 175 ma csns leakage current in off state (csnsx_en = 0, csns_ratio bit_x = 0) i csr_leak -4.0 ? +4.0 a systematic offset error (see current sense errors ) i _load_err_sys ? 15 ? ma random offset error i _load_err_rand -360 ? 360 ma csns pin current sourcing c apability, absolute upper limit i csns,max 5.15 ? ? ma e sr0 output current sensing error (%, uncompensated (15) ) at output current level (sense ratio c sr0 selected): t j =-40 q c 9.0 a 4.5 a 2.25 a 1.13 a t j =125 q c 9.0 a 4.5 a 2.25 a 1.13 a t j =25 to 125 q c 9.0 a 4.5 a 2.25 a 1.13 a e sr0_err -13 -12 -17 -31 -10 -9.0 -12 -19 -10 -9.0 -12 -22 ? ? ? ? ? ? ? ? ? ? ? ? 13 12 17 31 10 9.0 12 19 10 9.0 12 22 % table 3. static electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 06XS4200 electrical ch aracteristics static electrical characteristics e sr0 output current sensing error (%, after offset compensation (14) ) at output current level (sense ratio c sr0 selected): t j =-40 q c 9.0 a 4.5 a 2.25 a 1.13 a t j =125 q c 9.0 a 4.5 a 2.25 a 1.13 a t j =25 to 125 q c 9.0 a 4.5 a 2.25 a 1.13 a e sr0_err (comp) -10 -10 -10 -10 -9.0 -8.0 -9.0 -9.0 -9.0 -8.0 -9.0 -9.0 ? ? ? ? ? ? ? ? ? ? ? ? 10 10 10 10 9.0 8.0 9.0 9.0 9.0 8.0 9.0 9.0 % e sr1 output current sensing error (%, uncompensated (15) ) at output current level (sense ratio c sr1 selected): t j =-40 q c 2.25 a t j =125 q c 2.25 a t j =25 to 125 q c 2.25 a e sr1_err -16 -12 -12 ? ? ? 16 12 12 % notes: 13. current sense ratio c srx = i csns / (i hs[x] +i _load_err_sys ) 14. see note (15) , but with i csns_meas obtained after compensation of i _load_err_rand (see activation and use of offset compensation ). further accuracy improvements can be obtained by performing a 1- or 2 point calibration 15. e srx_err =(i csns_meas / i csns_model ) -1, with i csns_model = (i(hs[x])+ i _load_err_sys ) * c srx , (i _load_err_sys defined above, see section current sense error model ). with this model, load current becomes: i(hs[x]) = i csns / csr x - i _load_err_sys table 3. static electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 06XS4200 electrical characteristics static electrical characteristics e sr1 output current sensing error (% after offset compensation (16) ) at output current level (sense ratio c sr1 selected): t j =-40 q c 2.25 a 0.75 a 0.375 a 0.225 a t j =125 q c 2.25 a 0.75 a 0.375 a 0.225 a t j =25 to 125 q c 2.25 a 0.75 a 0.375 a 0.225 a e sr1_err (comp) -10 -11 -18 -29 -8.0 -10 -12 -16 -8.0 -10 -13 -21 ? ? ? ? ? ? ? ? ? ? ? ? 10 11 18 29 8.0 10 12 16 8.0 10 13 21 % e sr0 output current sensing error in parallel mode (%, uncompensated (17) ) at outputs current level (sense ratio c sr0 selected): t j =-40 q c 9.0 a 4.5 a t j =125 q c 9.0 a 4.5 a t j =25 to 125 q c 9.0 a 4.5 a e sr0_err_par -10 -11 -8.0 -8.0 -8.0 -8.0 ? ? ? ? ? ? 10 11 8.0 8.0 8.0 8.0 % notes: 16. see note (17) , but with i csns_meas obtained after compensation of i _load_err_rand (see activation and use of offset compensation ). further accuracy improvements can be obtained by performing a 1- or 2 point calibration. 17. e srx_err =(i csns_meas / i csns_model ) -1, with i csns_model = (i(hs[x])+ i _load_err_sys ) * c srx , (i _load_err_sys defined above, see section current sense error model ). with this model, load current becomes: i(hs[x]) = i csns / csr x - i _load_err_sys table 3. static electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data 13 freescale semiconductor 06XS4200 electrical characteristics static electrical characteristics electrical characteristics of the output stage (hs0 and hs1) (continued) current sense clamping voltage (condition: r(csns) > 10 kohm) v cl(csns) 5.5 ? 7.5 v open-load detection current threshold in off state (18) i old(off) 30 ? 100 p a open-load fault detection voltage threshold (18) v old(thres) 4.0 ? 5.5 v open-load detection current threshold in on state (see open-load detection in on state (ol_on) ): csns_ratio bit = 0 csns_ratio bit = 1 (fast slew rate sr[1:0] = 10 mandatory for this function) i old(on) 200.0 5.0 500.0 7.0 999.9 10 ma time period of the periodically activa ted open-load in on state detection for csns_ratio bit = 1 t olled 105 150 195 ms output shorted-to-v pwr detection voltage threshold (channel in off state) v osd(thres) v pwr -1.2 v pwr -0.8 v pwr -0.4 v switch turn-on threshold for negative output voltages (protects against negative transients) - (measured at i out = 100 ma, channel in off state) v cl -35 ? -24 v switch turn-on threshold for negative output voltages difference from one channel to the other in parallel mode - (measured at i out = 100 ma, channel in off state) ' v cl -2.0 ? +2.0 v switching state (on/off) discrimination thresholds v hs_th 0.45*v pwr 0.5*v pwr 0.55*v pwr v shutdown temperature (power mosfet junction; 6.0 v < v pwr < 58 v) t sd 160 175 190 q c notes: 18. minimum required value of open-load impedance for detection of open-load in off-state: 200 k : .(v old(thres) = v hs @ i old(off) ) table 3. static electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 06XS4200 electrical characteristics static electrical characteristics electrical characteristics of the control interface pins logic input voltage, high (19) v ih 2.0 ? 5.5 v logic input voltage, low (19) v il -0.3 ? 0.8 v wake-up threshold voltage (in[0:1] and rstb) (20) v wake 1.0 ? 2.2 v internal pull-down current source (on inputs: clock, sclk and si) (21) i dwn 5.0 ? 20 p a internal pull-up current source (input csb) (22) i up_csb 5.0 ? 20 p a internal pull-up current source (input conf[0:1]) (23) i up_conf 25 ? 100 p a capacitance of so, fsb and fsob pins in tri-state c so ? ? 20 pf internal pull-down resistance (rstb and in[0:1]) r dwn 125 250 500 k : input capacitance (24) c in ? 4.0 12 pf electrical characteristics of the control interface pins (continued) so high-state output voltage (i oh = 1.0 ma) v soh v dd -0.4 ? ? v sync, so, fsob and fsb low-state output voltage (i ol = -1.0 ma) v sol ? ? 0.4 v sync, so, csns, fsob and fsb tri-state leakage current: ( 0 v < v(so) < v dd , or v(fs) or v(sync) = 5.5 v, or v(fso) = 36 v or v(csns) = 0 v) i so(leak) - 2.0 0 2.0 p a conf[0:1]: required values of the external pull-down resistor lighting applications dc motor applications r conf 1.0 50 ? ? 10 infinite k : notes 19. high and low voltage ranges apply to si, csb, sclk, rstb, in [0:1] and clock input signals. the in[0:1] signals may be derive d from v pwr and can tolerate voltages up to 58 v. 20. voltage above which the device will wake-up 21. valid for v si > 0.8 v and v sclk > 0.8 v and v clock > 0.8 v. 22. valid for v csb < 2.0 v. csb has an internal pull-up current source derived from v dd 23. pins conf[0:1] are connected to an internal current source, derived from an internal voltage regulator (v reg ~ 3.0 v). 24. input capacitance of si, csb, sclk, rstb, in[0:1], conf[0:1 ], and clock pins. this parameter is guaranteed by the manufactur ing process but is not tested in production. table 3. static electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c, v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 06XS4200 electrical ch aracteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c,v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit output voltage switching characteristics rising and falling edge medium slew rate (sr[1:0] = 00) (25) v pwr = 16 v v pwr = 28 v v pwr = 36 v sr r_00 sr f_00 0.164 0.28 0.34 ? ? ? 0.65 0.79 0.90 v/ p s rising edge low slew rate (sr[1:0] = 01) (25) v pwr = 16 v v pwr = 28 v v pwr = 36 v sr r_01 sr f_01 0.081 0.14 0.17 ? ? ? 0.32 0.395 0.45 v/ p s rising edge high slew rate / sr[1:0] = 10) (25) v pwr = 16 v v pwr = 28 v v pwr = 36 v sr r_10 sr f_10 0.29 0.55 0.68 ? ? ? 1.30 1.58 1.80 v/ p s rising/falling edge slew rate matching per channel 16 v < v pwr < 36 v sr r /sr f 0.75 ? 1.2 edge slew rate difference from one channel to the other in parallel mode (25) 16 v < v pwr < 36 v sr[1:0] = 00 sr[1:0] = 01 sr[1:0] = 10 ' sr -0.1 -0.06 -0.14 0.0 0.0 0.0 +0.1 +0.06 +0.14 v/ p s output turn-on and turn-off delays (medium slew rate: sr[1:0] = 00) (26) 16 v < v pwr < 36 v t dly_00 39 - 145 p s output turn-on and turn-off delays (low slew rate / sr[1:0] = 01) (26) 16 v < v pwr < 36 v t dly_01 50 - 280 p s output turn-on and turn-off delays (high slew rate / sr[1:0] = 10) (26) 16 v < v pwr < 36 v t dly_10 22 - 80 p s turn-on and turn-off delay time matching per channel (t dly(on) - t dly(off) ) f pwm = 400 hz, 16 v < v pwr < 36 v , duty cycle on in[x] = 50 %, sr[1:0] = 00 ' t rf_00 -25 0.0 25 p s turn-on and turn-off delay time matching per channel (t dly(on) - t dly(off) ) f pwm = 200 hz, 16 v < v pwr < 36 v , duty cycle on in[x] = 50 %, sr[1:0] = 01 ' t rf_01 -60 0.0 60 p s turn-on and turn-off delay time matching per channel (t dly(on) - t dly(off) ) f pwm = 1.0 khz, 16 v < v pwr < 36 v , duty cycle on in[x] = 50 %, sr[1:0] = 10 ' t rf_10 -13 0.0 13 p s notes 25. rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 : resistive load (see figure 4 ). 26. turn-on delay time measured as delay between a rising edge of the channel control signal (in[0 : 1] = 1) and the associated rising edge of the output voltage up to: v hs[0 : 1] = v pwr / 2 (where r l = 5.0 : ). turn-off delay time is measured as time between a falling edge of the channel control signal (in[0 : 1] = 0) and the associated falling edge of the output voltage up to the instant at which: v hs[0 : 1] = v pwr / 2 (r l = 10.0 : )
analog integrated circuit device data 16 freescale semiconductor 06XS4200 electrical characteristics dynamic electrical characteristics switching characteristics (continued) delay time difference from one channel to the other in parallel mode (27) 16 v < v pwr < 36 v sr[1:0] = 00 sr[1:0] = 01 sr[1:0] = 10 ' t (dly) -41 -21 -12 0.0 0.0 0.0 41 21 12 p s fault detection delay time (28) t fault ? 5.0 8.0 p s output shutdown delay time (29) t detect ? 12.0 17 p s current sense output settling time for sr[1:0] = 00 (medium slew rate) (30) 16 v < v pwr < 36 v t csnsval_00 0.0 - 200 p s current sense output settling time for sr[1:0] = 01(low slew rate) (30) 16 v < v pwr < 36 v t csnsval_01 0.0 - 315 p s current sense output settling time for sr[1:0] = 10 (high slew rate) (30) 16 v < v pwr < 36 v t csnsval_10 0.0 - 165 p s sync output signal delay for sr[1:0] = 00 (medium sr) (30) t syncval_00 46 - 155 p s sync output signal delay for sr[1:0] = 01 (low sr) (30) t syncval_01 55 - 280 p s sync output signal delay for sr[1:0] = 10 (high sr) (30) t syncval_10 22 - 80 p s recommended sync_to_read delay sr[1:0] = 00 (medium slew rate) (30) t synread_00 0.0 - 200 s recommended sync_to_read delay sr[1:0] = 01 (low slew rate) (30) t synread_01 0.0 - 200 s recommended sync_to_read delay sr[1:0] = 10 (high slew rate) (30) t synread_10 0.0 - 200 s upper over-current threshold duration t och1 t och2 6.0 12.0 8.6 17.2 11.2 22.4 ms medium over-current threshold duration (conf = 0; lighting profile) t ocm1_l t ocm2_l 48 96 67 137 87 178 ms medium over-current threshold duration (conf = 1; dc motor profile) t ocm1_m t ocm2_m 150 301 214 429 278 557 ms frequency & pwm duty cycle ranges (31) (protections fully operational, see protective functions ) switching frequency range - direct inputs f control 0.0 ? 1000 hz switching frequency range - external clock with internal pwm (recommended) f pwm_ext 20 ? 1000 hz switching frequency range - internal clock with internal pwm (recommended) f pwm_int 60 ? 1000 hz duty cycle range r control 0.0 ? 100 % notes: 27. rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 : resistive load (see figure 4 ). 28. time required to detect and report the fault to the fsb pin. 29. time required to switch off the channel after detection of over -temperature (ot), over-current (oc), sc or uv error (time me asured between start of the negative edge on the fsb pin and the falling edge on the output voltage until v(hs[0:1)) = 50% of v pwr 30. settling time ( = t csnsval_xx ), sync output signal delay ( = t syncval_xx ) and read-out delay ( = t synread_xx ) are defined for a stepped load current (100 ma< i(load) analog integrated circuit device data freescale semiconductor 17 06XS4200 electrical ch aracteristics dynamic electrical characteristics availability diagnostic functions o ver duty-cycle and switching frequency (protections & diagnostics both fully operational, see diagnostic features for the exact boundary values) available duty cycle range, f pwm = 1.0 khz high slew rate, pwm mode (32) ol_off ol_on os r pwm_1k_h 0.0 35 0.0 ? ? ? 62 100 90 % available duty cycle range, f pwm = 400 hz, medium slew rate, pwm mode (32) ol_off ol_on os r pwm_400_m 0.0 21 0.0 ? ? ? 81 100 88 % available duty cycle range, f pwm = 400 hz, high slew rate, pwm mode (32) ol_off ol_on os r pwm_400_h 0.0 14 0.0 ? ? ? 84 100 95 % available duty cycle range, f pwm = 200 hz, low slew rate mode, pwm mode (32) ol_off ol_on os r pwm_200_l 0.0 15 0.0 ? ? ? 86 100 93 % available duty cycle range, f pwm = 200 hz, medium slew rate, pwm mode (32) ol_off ol_on os r pwm_200_m 0.0 11 0.0 ? ? ? 90 100 94 % available duty cycle range, f pwm = 100 hz in low slew rate, pwm mode (32) ol_off ol_on os r pwm_100_l 0.0 8.0 0.0 ? ? ? 93 100 96 % deviation of the internal clock pwm frequency after calibration (33) a fpwm(cal) -10 ? +10 % default output frequency when using an uncalibrated oscillator f pwm(0) 280 400 520 hz minimal required low time during calibr ation of the internal clock through csb t csb(min) 1.0 1.5 2.0 p s maximal allowed low time during calibration of the internal clock through csb t csb(max) 70 100 130 p s recommended external clock frequency range (external clock/pwm module) f clock 15 ? 512 khz upper detection threshold for ex ternal clock frequency monitoring f clock(max) 512 730 930 khz lower detection threshold for ex ternal clock frequency monitoring f clock(min) 5.0 7.0 10 khz notes 32. actually, the device can be operated outsi de the specified duty cycle and frequency ranges (basic protective functions oc, s c, uv, ov, ot remain active) but the availability of the di agnostic functions ol_on, ol_off, os is affected. 33. values guaranteed from 60 hz to 1.0 khz (recommended switching frequency r ange for internal clock operation). table 4. dynamic electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c,v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data 18 freescale semiconductor 06XS4200 electrical characteristics dynamic electrical characteristics timing: spi port, in[0]/ in[1] signals & autoretry required low time allowing delatching or triggering sleep mode (direct input mode) t in 175 250 325 ms watchdog timeout for entering fail-safe mode due to loss of spi contact (34) t wdto 217 310 400 ms auto-retry repetition period (when activated): auto_period bits = 00 auto_period bits = 01 auto_period bits = 10 auto_period bits = 11 t auto_00 t auto_01 t auto_10 t auto_11 105 52.5 26.2 13.1 150 75 37.5 17.7 195 97.5 47.8 24.4 ms gnd pin temperature sensing function thermal prewarning detection threshold (35) t otwar 110 125 140 c temperature sensing output voltage @ t a = 25 c (470 : < r csns < 10 k : t feed 918 1078 1238 mv gain temperature sensing output @ t a = 25 c (470 : < r csns < 10 k : (35) dt feed 10.7 11.1 11.5 mv/c temperature sensing error, range [-40 c, 150 c], default (35) t feed_error -15 ? +15 c temperature sensing error, [-40 c, 150 c] after 1 point calibration @ 25 c (35) t feed_error_ cal -5.0 ? +5.0 c notes 34. only when the wd_dis bit set to logic [0] (default). watc hdog timeout defined from the rising edge on rst to rising edge hs[ 0,1] 35. values were obtained by lab characterization. table 4. dynamic electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c,v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data freescale semiconductor 19 06XS4200 electrical ch aracteristics dynamic electrical characteristics spi interface electrical characteristics (36) maximum operating frequency of the serial peripheral interface (spi) (37) f spi ? ? 8.0 mhz required low-state duration for reset rstb (38) t wrstb 10 ? ? p s required duration from the rising to the falling edge of csb (required setup time) (39) t csb 1.0 ? ? p s rising edge of rstb to falling edge of csb (required setup time) (39) t enbl 5.0 ? ? p s falling edge of csb to rising edge of sclk (required setup time) (39) t lead 500 ? ? ns falling edge of sclk to rising edge of csb (required setup lag time) (39) t lag 60 ? ? ns required high state duration of sclk (required setup time) (39) t wsclkh 50 ? ? ns required low state duration of sclk (required setup time) (39) t wsclkl 50 ? ? ns si to falling edge of sclk (required setup time) (40) t si (su) 15 ? ? ns falling edge of sclk to si (required hold time of the si signal) (40) t si (h) 30 ? ? ns so rise time c l = 80 pf t rso ? ? 20 ns so fall time c l = 80 pf t fso ? ? 20 ns si, csb, sclk, max. rise time allowing operation at f spi = 8.0 mhz (40) t rsi ? ? 11 ns si, csb, sclk, max. fall time allowing operation at f spi = 8.0 mhz (40) t fsi ? ? 11 ns time from rising edge of sclk to reach a valid level at the so pin (41) t valid ? ? 44 ns time from falling edge of csb to reach low-impedance on so (access time) (42) t soen ? ? 30 ns time from rising edge of csb to reac h high-impedance on so pin (turn off time) t sodis 30 ns notes: 36. parameters guaranteed by design. it is recommended to tie unused spi-pins to gnd by resistors 1.0 k 4.0 mhz, series resistors on the spi pins should preferably be removed. otherwise, 470 pf (v max. > 40 v) ceramic speed-up capacitors in parallel with the >8.0 k : input resistors are required on pins sclk, si, so, cs 38. rstb low duration is defined as the minimum time required to switch off the channel w hen previously put on in spi mode (direct inputs inactive). 39. minimum setup time required for the device is the minimum requi red time that the microcontroller must wait or remain in a gi ven state. 40. rise and fall time of incoming si, csb, and sclk signals. 41. time required for output data to be avail able for use at so, measured with a 80 pf capacitive load. 42. time required for output data to be terminat ed at so measured without a series resistor connected csb. table 4. dynamic electrical characteristics (continued) unless specified otherwise: 8.0 v d v pwr d 36 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v. typical values are average values evaluated under nominal conditions t a = 25 c,v pwr = 28 v & v dd = 5.0 v, unless specified otherwise. parameter symbol min typ max unit
analog integrated circuit device data ? 20 freescale semiconductor 06XS4200 electrical characteristics timing diagrams timing diagrams v pwr v hs[0:1] t dly_xx t dly_xx low logic level 80% v pwr 20% v pwr sr f sr r 50%v pwr r pwm range defined for 50% of v pwr csb high logic level v hs[0:1] time time time low logic level in[0:1] high logic level time or (t dly(on) ) (t dly(off) ) figure 4. output voltage slew rate and delay i och 1 t ocm2_l t ocm1_l t och1 time load current i och2 i ocm1 i ocl1 i ocl2 i ocm2 t och2 bulb profile: confs = 0 (v (pin 5/6) <0.8 v). static over-current protection profile activated once per turn-on. default levels shown as solid lines i ocl3 figure 5. over-current protection profile for bulb applications
i och 1 t ocm2_m t ocm1_m t och1 time load current i och2 i ocl1 i ocl2 t och2 inductive load profile: confs = 1 (v (pin 5/6) > 2.0 v) default levels shown as solid lines dynamic over-current window, activated when the i oclx threshold is crossed load current i ocl3 analog integrated circuit device data ? freescale semiconductor 21 06XS4200 electrical ch aracteristics timing diagrams figure 6. over-current protection profile for app lications with inductive loads (dc motors, solenoids) rstb csb sclk si don?t care must be valid don?t care v ih v il t wrstb v ih v il v ih v il v ih v il must be valid t enbl 10% v dd 10% v dd t lead t wsclkh 90% v dd 10% v dd t rsi 90% v dd t csb t lag t fsi t wsclkl t si(su) t si(h) 90% v dd 10% v dd don?t care v ih v il so t soen tri-stated tri-stated t sodis figure 7. timing requirements during spi communication
sclk so v oh v ol t valid 90% v dd 10% v dd so high to low low to high v ol v ol v oh v oh t rsi t fsi 50% 10% v dd 90% v dd t rso t fso 10% v dd analog integrated circuit device data ? 22 freescale semiconductor 06XS4200 electrical characteristics timing diagrams figure 8. timing diagram for serial output (so) data communication v pwr v hs[0:1] t dly_xx t dly_xx 50%v pwr time turn-on v csns time 95% of scaled time 5.0 v 0.0 v v sync turn-off control control t csnsval_xx t syncval output current track & hold mode synchronous mode ( t dly(on) ) ( t dly(off ) (from in_s or csb) (from in_s or csb) t synread_xx see figure 3 figure 9. synchronous & track-and-hold current sensing modes: associated delay & settling times
analog integrated circuit device data freescale semiconductor 23 06XS4200 functional description introduction functional description introduction the 06XS4200 is a two-channel, 24 v high side switch with integrated control and diagnostics designed for truck, bus, and industrial applications. the device provides a high number of protective functions. both low r ds(on) channels (<6.0 m : ) can independently drive various load types like light bulbs, solenoid actuators, or dc motors. device control and diagnostics are configured through a 16-bit spi port with daisy chain capability. independently programmable out put voltage slew rates allow satisfying electromagnetic compatibility (emc) requirements. both channels can independently be operated in several different switching modes: internal clock, internal pwm mode (fully autonomous operation), external clock, and direct control switching mode. current sensing with an adjustable ratio is available on both channels, allowing both high current (bulbs) and low current (led) monitoring. by activating the track & hold mode, current monitoring can be performed during the switch-off phase. this allows random access to the current sense functionality. a pate nted offset compensation technique further enhances current sense accuracy. to avoid turning off during inrush current, while being able to monitor it, the device feat ures a dynamic over-current threshold profile. for bulbs, this profile is a stair function with stages of which the height and width are programmable through the spi port. dc motors can be protected from overheating by activating a specific window-shaped over- current profile that allows st all currents of limited duration. whenever communication with the external micro- controller is lost, the device enters fail-safe operation mode, but remains operational, controllable and protected. pin assignment and functions functions and register bi ts that are implemented independently for both channels have extension ?_s?. max. ratings of the pins are given in table 2 . output current monitoring (csns) the csns pin allows independent current monitoring of channel 0 or channel 1 up to th e steady-state over-current threshold. it can also be used to sense the device temperature. the different func tions are selected by setting bits csns1_en and csns0_en to the appropriate value ( table 11 ). when the csns pin is sensed during switch-off in the (optional) track & hold mode, it will output the scaled value of the load current as it was just before turn-off. when several devices share the same pull-down resistor, the csns pins of unused devices must be tri-stated. this is accomplished by setting csns0_en = 0 and csns1_en = 0 in the gcr register. settling time (t csnsval_xx ) is defined as the time between the instant at the middle of the output voltage?s rising edge (hs[0:1] = 50% of v pwr ), and the instant at which the voltage on the csns-pin has settled to 5.0% of its final value. anytime an over-current window is active, the csns pin is disabled (see over-current detection on resistive and inductive loads ). the current and temperature sensing functions are unavailable in fail-safe mode and in normal mode when operating without the v dd supply voltage. in order to generate a voltage output, a pull- down resistor is required (r(csns)=1.0 k : typ. and 470 < r(csns) < 10 k). when the current sense resistor connected to the csns pin is disconnected, the csns voltage is clamped to v cl(csns) . the csns pin can source currents up to about 5.6 ma. current sense synchronization (sync) to synchronize current sensing with an external process, the sync signal can be connected to a digital input of an external mcu. sync is asserted logic low when the current sense signal is accurate and ready to be read. the current sense signal on the csns pin has the specified accuracy t synread_xx seconds after the falling edge on the sync pin ( figure 9 ) and remains valid until a rising edge is generated. the rising edge that is generated by the sync pin at the turn- off instant (internal or external) may also be used to implement synchronization with the external mcu. parameter t syncval_xx is defined as the time between the instant at the middle of the output-voltage rising edge (hs[0:1] = 50% of v pwr ), and the instant at which the voltage on the sync-pin drops below 0.4 v (v sol ). the sync pins of different devices can be conne cted together to save micro- controller input channels. howeve r, in this configuration, the csns function of only one device should be active at a time. otherwise, the mcu will not be ab le to determine the origin of the sync signal. the sync pin is open drain and requires an external pull-up resistor to v dd . direct control inputs (in0 and in1) the in[0:1] pins allow direct control of both channels. a logic [0] level turns off the channel and a logic[1] level turns it on ( channel control in normal mode ). when the device is in sleep mode, a transition from logic 0 to logic 1 on any of these pins will wake it up ( sleep mode ). if it is desired to automatically turn on the channels after a transition to fail- safe mode, inputs in[0] and in[1] must be externally connected to the vpwr pin by a pull-up resistor (e.g. 10 k : typ . however, this will prevent the device from going into
analog integrated circuit device data 24 freescale semiconductor 06XS4200 functional description pin assignment and functions sleep mode. both in pins are internally connected to a pull- down resistor. configuration inputs (conf0 and conf1) the conf[0 :1] input pins allow configuring both channels for the appropriate load type. conf = 0 activates the bulb over-current protection profile, and conf = 1 the dc motor profile. these inputs are connected to an internal voltage regulator of 3.3 v by an internal pull-up current source i up . therefore, conf = 1 is the default value when these pins are disconnected. details on how to configure the channels are given in the table over-current profile selection . fault status (fsb) this open-drain output is asserted low when any of the following faults occurs (see fault mode ): over-current (oc), over-temperature (ot), output connected to v pwr , severe short-circuit (sc), open-load in on state (ol_on), open- load in off state (ol_off), external clock-fail (clock_fail), over-voltage (o v), and under-voltage (uv). each fault type has its own assigned bit inside the statr, faultr_s, or diagr_s regist er. fault type identification and fault bit reset are accomplished by reading out these registers. they are part of the so register ( table 12 ) and are accessed through the spi port. pwm clock (clock) this pin is the input for an external clock signal that controls the internal pwm module.the clock signal is monitored by the device. the pwm module controls on-time and turn-on delay of the selected channels. the clock pin should not be confused with t he sclk pin, which is the clock pin of the spi interface. clock has an internal pull-down current source (i dwn ) to gnd. reset (rstb) all spi register contents are reset when rstb = 0. when rstb = 0, the device returns to sleep mode t in sec. after the last falling edge of the last acti ve in[0:1] signal. as long as the reset input (rstb pin) is at logic 0 and both direct input states are low, the device remains in sleep mode ( channel configuration through the spi ). a 0-to-1 transition on rstb wakes up the device and starts a watchdog timer to check the continuous presence of the spi signals. to do this, the device monitors the contents of the fi rst bit (wdin bit) of all spi words following that transition (regardless the register it is contained in). when this contents is not alternated within a duration t wdto , spi communication is considered lost, and fail-safe mode is entered ( entering fail-safe mode ). rstb is internally pulled-down to gnd by resistor r dwn . chip select (csb) data communication over the spi port is enabled when the csb pin is in the logic [0] stat e. data from the input shift registers are locked in the a ddressed si registers on the rising edge of csb . the device transfers the contents of one of the 8 internal registers to the so register on the falling edge of csb . the so output driver is enabled when csb is logic [0]. csb should transition from a logic [1] to a logic [0] state only when sclk is at logic [0] ( figure 7 and figure 8 ). csb is internally pulled up to v dd through i up . spi serial clock (sclk) the sclk pin clocks the spi data communication of the device. the serial input pin (si) transfers data to the si shift registers on the falling edge of the sclk signal while data in the so registers are transferred to the so pin on the rising edge of the sclk signal. the sclk pin must be in the low state when csb makes any transition. for this reason, it is recommended to have the sclk pin in the logic [0] state when the device is not accessed ( csb is at logic [1]). when csb is set to logic [1], signals at the sclk and si pins are ignored and the so output is tri-stated (high-impedance). the sclk pin is connected to an internal pull-down current source i dwn . serial input (si) serial input (si) data bits are shifted in at this pin. si data is read on the falling edge of sclk. 16-bit data packages are required on the si pin (see figure 7 ), starting with bit d15 (msb) and ending with d0 (lsb). all the internal device registers are addressed and controlled by a 4-bit address (d9-d12) described in table 10 . register addresses and function attribution are described in table 11 . the si pin is internally connected to a pull-down current source, i dwn . supply of the digital circuitry (vdd) this pin supplies the spi circuit (3.3 v or 5.0 v). when lost, all circuitry becomes supplied by a v pwr derived voltage, except the spi?s so sh ift-register that can no longer be read. ground (gnd) this is the gnd pin common for both the spi and the other circuitry. positive supply pin (vpwr) this pin is the positive supply and the common input pin of both switches. a 100 nf ceramic capacitor must be connected between vpwr and gnd, close to the device. in addition, it is recommended to put a ceramic capacitor of at least 1.0 f in parallel with this 100 nf capacitor. serial output (so) the so pin is a tri-stateable output pin that conveys data from one of the 13 internal so registers or from the previous si register to the outside world. the so pin remains in a high- impedance state (tri-state) until the csb pin becomes logic [0]. it then transfers the spi data (device state, configuration, fault information) . the so pin changes state at the rising edge of the sclk signa l. for daisy-chaining, it can be read out on the falling edge of sclk. v dd must be present
analog integrated circuit device data ? freescale semiconductor 25 06XS4200 functional description functional internal block description before the so registers can be read. the so register assignment is described in ta b l e 12 . power switch output pins (hs0 and hs1) hs0 and hs1 are the output pins of the power switches, to be connected to the loads. a ceramic capacitor (<= 22 nf (+/ - 20%) is recommended between these pins and gnd for optimal emc performances. fail-safe output (fsob) this pin (active low) is used to indicate loss of spi communication or loss of spi supply voltage, v dd. this open- drain output requires an external pull-up resistor to vpwr. functional internal block description power supply mcu interface and output control spi interface parallel control inputs pwm controller self- protected high side switches hs0-hs1 mcu interface internal regulator power supply the device will operate with supply voltages from 6.0 to 58 v (v pwr ), but will be full spec. compliant only between 8.0 and 36 v. the vpwr pin supplies power to the internal regulator, analog, a nd logic circuit blocks. the vdd pin (5.0 v typ .) supplies the output register of the serial peripheral interface (spi). consequently, the spi registers cannot be read without presence of v dd . the employed ic architecture guarantees a low quiescent current in sleep mode. switch output pins hs0 & hs1 hs0 and hs1 are the output pi ns of the power switches. both channels are protected against various kinds of short- circuits and have active clamp circuitry that may be activated when switching off inductive loads. many protective and diagnostic functions are available. for large inductive loads, it is recommended to use a freewheeling diode. the device can be configured to control t he output switches in parallel, which guarantees good switching synchronization. communication interface and device control in normal mode the output channels can either be controlled by the direct inputs or by the internal pwm module, which is configured by the spi register settings. for bidirectional spi communication, v dd has to be in the authorized range. failure diagnostics and configuration are also performed through the spi port. the reported failure types are: open-load, short-circ uit to battery, severe short- circuit to ground, over-current , over-temperature, clock-fail, and under and over-voltage. the spi port can be supplied either by a 5.0 v or by a 3.3 v voltage supply. for direct input control , v dd is not required. a pulse width modulation (pwm) circuit allows driving lo ads at frequencies up to 1.0 khz from an external or an in ternal clock. spi communication is required to set these options.
analog integrated circuit device data 26 freescale semiconductor 06XS4200 functional device operation operation and operating modes functional device operation operation and operating modes the device possesses two high side switches (channels) each of which can be controlled independently. the device has four fundamental operating modes: sleep, normal, fail- safe, and fault mo de, as shown in table 5 . each channel can be controlled in three different ways in normal mode: by a signal on the direct input pin, by an internal clock signal (autonomous operation) or by an external clock signal. for bidirectional spi communication, a second supply voltage is required (v dd = 5.0 v or 3.3 v). when only the direct inputs in[x] are used, v dd isn?t required. device start-up sequence to put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. however, it should not be woken up earlier than the moment at which v pwr has exceeded its under-voltage threshold, v pwr (uv), and v dd has exceeded its supply failure threshold, v dd (fail). in applications using the spi port, the device is typically put in wake mode by setting rstb=1. wake-up of applications with direct input control can be achieved by having signals in_on[0] = 1 or in_on[1 ]= 1 (see figure 10 ). after wake-up, all spi register contents are reset (as defined in table 11 and table 12 ) and normal mode is entered. all the device functions will be available 50 s later (typically). if the start-up sequence is not performed at device start- up, its configuration may be undetermined and correct operation is not guaranteed. in situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up event after the moment v pwr has reached the under-voltage threshold. channel configuration through the spi setting the channe l configuration the channel configuration is de termined by the contents of the pulse-width (pwmr_s), the configuration (confr_s) and the over-current (ocr_s) r egisters. they allow setting, among others, the fo llowing parameters: du ty-cycle, delay, slew rate, pwm enable (p wm_en), clock selection (clock_sel), prescaler (pr), and direct_input disable (dir_dis). extension ?_s? means that these registers exist for each of both channels. function assignment is described in detail in the section si register addressing . reading back the channel?s status and settings the channel?s global switchi ng and operating states (on/ off, normal/fault) are all contained in the so-statr register (see table 12 ). the precise fault type can be found by reading out the faultr_s and statr registers. the current channel settings (channel configuration) can be known by reading the pwmr, conf, ocr, retryr, gcr, and diag registers (see section serial output register assignment and further). normal mode normal mode (bit nm = 1) can be entered in two ways: either by driving the device through the direct inputs (in[x]) or by establishing spi communication (requires rstb =high). bidirectional spi communicatio n additionally requires the presence of v dd . to maintain the device in normal mode, communication must take place regularly (see entering and maintaining normal mode ). the device is in normal mode (nm) when: ?v pwr (and v dd ) are within the normal range and ? wake-up = 1, and ? fail-safe = 0, and ? fault = 0. channel control in normal mode in direct input mode, the channel?s switching state (on/off) is controlled by the logic state of the direct input signal with the default values (00) of turn-on delay and slew rate, specified in table 4 . in internal clock mode, the s witching state is controlled by an internal clock signal ( internal clock & internal pwm (clock_int_s bit = 1) ). frequency, slew rate, duty-cycle, and turn-on delay are programmable independently for both channels. in external clock mode, the frequency of the external clock controls the output's pwm frequency, but slew rate, duty cycle, and turn-on delay are still programmable. factors determining the channel?s switching state the switching state of a ch annel is defined by the instantaneous value of the output voltage. it is defined as ?on? when the output vo ltage v(hs[x]) > v pwr /2 and ?off? when v(hs[x]) < v pwr /2. the channel?s switching state should not be confused with the device?s internal channel control state hson[x] (= high side on). signal hson[x] defines the targeted switching state of the channel (on/off). it is either controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the spi register settings. the value of hson[x] is given by the following boolean expression: hson[x] = [(in[x] and dir_dis[x] ) or (on bit [x] and duty_cycle[x] and pwm_en[x] = 1) or (on bit [x] and pwm_en[x] = 0)]. in this expression duty_cycle[x] represents the value of the duty cycle, set by bits d7?d0 of the pwmr register
analog integrated circuit device data ? freescale semiconductor 27 06XS4200 functional device operation operation and operating modes ( table 6 ). the channel?s actual switching state may differ from the control signal?s state in the following cases: ? short circuits to gnd, before automatic turn-off (t < t fault ) ? short circuits to v pwr when the channel is set to off ?v pwr < 13 v when open-load-in-off-state detection is sele cted and the load is actually lost ? during the turn-on transition as long as v(hs[x])< vpwr/2 ? during the turn-off transition as long as v(hs[x]) > vpwr/2 entering and maintaining normal mode a 0-to-1 transition on rstb, (when both v pwr and v dd are present) or on any of both di rect inputs in[x] (when only supplied by v pwr ) will put the device in normal mode. if desired, the device can be op erated in normal mode without v dd , but this requires that at leas t one of both direct inputs be regularly turned on ( operation and operating modes ). to maintain the device in norm al mode (nm), communication must take place on a regular basis. for spi communication, the stat e of the wdin bit must be alternated at least every 310 ms (typ.) (t wdto ), unless the wd_disable bit is set to 1. for direct input control, the timing requirements are shown in figure 10 . a signal called in_on[x] is not directly accessible to the user but is used by the i nternal logic circuitry to determine the device state. when no activity is detected on a direct input pin (in[x]) for a time longer than t in = 250 ms (t yp.), timeout is de tected and in_on[x] goes low. when this occurs on both channels, sleep mode is entered ( sleep mode ), provided reset = rstb = 0 it will enter fail-safe mode in case of a timeout on spi communica tion or when v dd is lost after having been initially present (if this function was previously enabled by setting: v dd _ fail _ en bit = [1]). setting watchdog disabled (wd_dis = 1, d4 of the gcr register) avoids entering fail- safe mode after watchdog timeout. device behavior upon fault occurrence is explained in the paragraph on faults ( fault mode ). in_on[x] in[x] t in . figure 10. relation between sign al s in(x) and in_on[x] direct control mode when rstb = 0 (and also in fail-safe mode), the chan nels are merely controlled by the direct input pins in[x]. all protective functions (oc, ot, sc, ov, uv) are operational including auto-retry. to avoid entering sleep mode at frequencies < 4.0 hz, reset should be set to rstb = 1. going from normal to fail-safe, fault or sleep mode the device changes from normal to fail-safe ( fail-safe mode ), sleep mode ( sleep mode ), or fault mode ( fault mode ), according to the value of the following signals (see table 5 ). ? wake-up = rstb or in_on[0] or in_on[1] ? fail-safe = (v dd failure and v dd _fail_en) or (spi watchdog timeout (t wdto ) and wd_dis = 0) ? fault = oc[0:1] or ot[0:1] or sc[0:1] or uv or (ov and ov_dis ) table 5. device operating modes mode wake-up fail- safe fault comments sleep 0 x x all channels are off. normal 1 0 0 the spi watchdog is active when: vdd = 5.0 v, wd_dis = 0, rst = 1 fail-safe 1 1 0 the channels are controlled by the in inputs. (see page 28 ) fault 1 x 1 the channels are off, see page 29. x = don?t care.
sleep (fail-safe = 0) and (wake-up = 1) and (fault = 0) (wake-up = 0) fail-safe normal (wake-up = 0) (fail-safe = 1) and (wake- up = 1) and (fault = 0) (fail-safe = 0) and (wake- up = 1) and (fault = 0) (wake-up = 1) and (fail-safe = 1) and (fault = 0) fault (wake-up = 0) (wake-up = 1) and (fault = 1) (fail-safe = 0) and (wake-up = 1) and (fault = 1) (fail-safe = 1) and (wake-up = 1) and (fault = 1) (fail-safe = 0) and (wake- up = 1) and (fault = 0) (fail safe = 1) and (wake-up = 1) and (fault = 0) analog integrated circuit device data ? 28 freescale semiconductor 06XS4200 functional device operation operation and operating modes figure 11. device operating modes sleep mode in sleep mode, the channels and the spi interface are turned off to minimize current consumption. the device enters sleep mode (wake-up = 0) when both direct i nput pins in(x) remain off longer than t in sec. (when reset is active; rstb = 0). this is expressed as follows: ?v pwr (and v dd ) are within the normal range, and ? wake-up = 0 (wake-up = rstb or in_on[0] or in _on[1]) ? and ? fail-safe = x and ?fault = x when employed, v dd must be kept in the normal range. sleep mode is the default mode after the first application of the supply voltage (v pwr ), prior to any i/o communication (rstb and the internal states in_on[0:1] are still at logic [0]). all spi regi ster contents remain in their default state during sleep mode. fail-safe mode entering fa il-safe mode fail-safe mode is entered either upon loss of spi communica tion or after loss of optional spi supply voltage v dd ( vdd out of range ). the fsob pin will go low and the channels are only be controlled by the direct inputs (in[0:1]). all protective functions remain fully operational. previously latched faults are delatched and spi register contents is reset (except bits por & parallel). the spi registers can not be accessed. these conditions are also described by the following expressions: ?v pwr is within the normal voltage range, and ? wake-up = 1, fault = 0, and ? fail-safe = 1 ((v dd failure and v dd _fail_en=1 before) or (t(spi)> t wdto and wd_dis = 0). the last condition describes the loss of spi communi cation which is detailed in the next section. watchdog on spi communication and fail-safe mode when v dd is present, the spi watchdog timer is started upon a rising edge on the rstb pin. thereafter the device monitors the state of the first bit (wdin) of all received spi words. when the state of this bit is not alternated at least once within a data stream of duration t wdto = 310 ms typ. , the device considers that spi communication has been lost and enters fail-safe mode. this behavior can be disabled by setting the bit wd_dis = 1. the value of watchdog timeout is de rived from an internal oscillator . returning from fail- s afe to normal mode to exit fail-safe mode and return to normal mode again, f irst a spi data word with its wdin bit = 1 (d15) must be recei ved by the device (regardless the register it is contained
analog integrated circuit device data freescale semiconductor 29 06XS4200 functional device operation operation and operating modes in and regardless the values of the other bits in this register). next, a second data word must be received within the timeout period (t wdto = 310 ms typ.) to be able to change any spi register contents. upon entering normal mode, the fsob pin returns to logic high and previously set faults and spi registers are reset, except bits por, parallel and fault bits of latchable faults t hat had actually been latched. fault mode the device enters fault mode when any of the following faults occurs in normal or fail-safe mode: ? over-temperature faul t, (latchable fault) ? over-current fault, (latchable fault) ? severe short-circuit fault, (latchable fault) ? output shorted to v pwr in off state (default: disabled) ? open-load fault in off state (default: disabled) ? open-load fault in on state (default: disabled) ? external clock failure (default: enabled) ? over-voltage fault (enabled by default) ? under-voltage fault, (latchable fault) the fault status pin ( fsb) asserts a fault occurrence on any channel in real time (a ctive low). additionally, the assigned fault bit in the statr_s or faultr_s register is set to one. conversely to the fsb pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. these bits can be read via the so pin. fault occurrence will also result in a turn-off of the incurred channel, except for the following faults: open-load (on and off state), external clock fail ure and output(s) shorted to v pwr . under and over-voltage occurrence will cause simultaneous turn-off of bot h channels. details on the device?s behavior after the occurrence of one of the above faults can be found in protection and diagnostic features . fault mode ( operation and operating modes ) is entered when: ?v pwr (+v dd ) were within the normal voltage range, and ? wake-up = 1, and ? fail-safe = x, and ?fault = 1 (see going from normal to fail-safe, fault or sleep mode ) resetting fault bits registers statr_s and faultr_s contain global and channel-specific fault information. reading the register where the fault bit is contained in will clear it, provided failure cause disappearance was detected and the fault wasn?t latched. entering fault mode from fail-safe mode when a fault occurs in fail-safe mode, the device is in fault/fail-safe mode and behaves according to the description of fault mode. ho wever, spi registers remain reset and can not be accessed. only the direct inputs control the channels. returning from fault mo de to fail-safe mode when disappearance of the fault previously produced in fail-safe mode has been detected, the device returns to fail- safe mode and behaves accordingly. fsb goes high, but the auto-retry counter is not rese t. latched faults are not delatched. spi registers remain reset. latchable faults an auto-retry function (see auto-retry ) controls how the device responds to the so-called latchable faults. latchable faults are: over-current (oc), severe short-circuit (sc), over- temperature (ot), and under-voltage (uv). if a latchable fault occurs, the channel is turned off, the fsb terminal goes low, and the assigned fault bit is set. these bits can not be reset before the next turn-on even t is generated by auto-retry. next, the channel will automat ically be turned on at a programmable interval (provided auto-retry was enabled and the channel wasn?t latched). if the failure disappears prior to the expiration of the available amount of auto-retries, the fsb pin automatically returns to logic [1], but the fault bit remains set. it can then still be reset by reading the spi r egister it is contained in. however, the fault actually gets latched if the failure cause hasn?t disappeared at the first turn-on event following expiration of the available amount of auto-retries (see auto- retry ). in that case, the channel gets latched and the fsb terminal remains low. the fault bit can not be reset by reading out the associated spi register prior to performing a delatch sequence ( fault delatching ). fault delatching to delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure caus e. delatching will also allow to reset the fault bit of latched faults (see resetting fault bits ). to reset the fsb pin, both channels must be delatched. delatching is achieved either by alternating the state of the channels? fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). see reset of the auto-retry counter . delatching then actually occurs at the rising edge of the turn- on event. signal fc[x] is an internal signal used by the device?s internal logic circuitry to control the diagnostic functions. the value of fc[x] depends on the st ate of the variables in_on[x], dir_dis[x] and on[x] and is expressed as follows: fc[x] = ((in_on[x] and dir_dis[x] = 0) or on[x] = 1) alternating the fc[x] signal is achieved differently according to the way the user controls the device. ? in direct-input controlled mode (dir_dis_s = 0), the in[x] pin must be set low, remain low for at least t in seconds, and set high again (be switched on). this might happen automatically when operating at frequencies f<4.0 hz. ? in spi-controlled mode, the on_bit state (d8 of the pwmr_s reg.) must be alternat ed (?toggled?). no minimum off state duration is required in this case.
analog integrated circuit device data ? 30 freescale semiconductor 06XS4200 functional device operation operation and operating modes performing a delatch sequence anytime during an ongoing auto-retry sequence (before latching) allows turning the channel on unconditionally. when a power-on event occurs (see loss of vpwr , loss of vdd and power-on-reset (por) ), latched channels are also delatched and faults are reset. when fail-safe mode is ent ered (fault=1, fail-safe becomes 1) during operating in fault mode (fault=1, failsafe=0), previously latched faults are delatched and spi register content is reset (exc ept bits por & parallel). the device is then in a combined fail-safe/fault mode. when the device was already in f ail-safe mode (fault=1, failsafe=1) and (new) faults occurs, the internal auto-retry counter will not be reset and latched channels will not be delatched until a delatching sequence has been performed (see protection and diagnostic features ). programmable pwm module each channel has a fully independent pwm module activated by setting pwm_en_s. it modulates an internal or external clock signal. setting clock_int_s = 1 (bit d6 of the ocr_s register) activates the in ternal clock, and setting clock_int_s = 0 activates the external clock. the duty cycle can be set in a range from 0% to 100% with 8 bit-resolution ( table 6 ) by setting bits d8?d0 of the pwmr_s register ( table 11 ). the channel?s switching frequency equals the clock frequency divided by 256 in internal clock mode, and by 256 or 512 in external clock mode. external clock frequency monitoring clock cs in_x internal clock calibration mux pr_x ??? (1 + pr_x clock_fail clock_sel_x internal oscillator ??? 25 pwm mode hs_x driver block pwmr_s register pwm_en_x vpwr hsx figure 12. internal and external clock operation table 6. pwm duty cycle value assignment on-bit duty cycle channel configuration 0 x off 1 00000000 pwm (duty cycle=1/256) 1 00000001 pwm (duty cycle=2/256) 1 00000010 pwm (duty cycle=3/256) 1 n pwm(duty cycle=(n+1)/256) 1 11111111 fully on . by delaying the activation of one channel relative to the other ( table 7 ), switch-on surges can be delayed, which may improve emc performance. switch-on delay can be selected among seven different values (default=0) by setting bits d2?d0 of the confr_s register (expressed as a number of ext./int. pwm clock periods). to start the pwm function at a known point in time, the pwm_en_s bit (d8 /d7 of the gcr reg.) must only be set to 1 after having set the pwmr_s (duty cycle) and confr_s (delay) r egisters. the best way to improve emc is to use an external clock with a staggered switch on delay. table 7. switch-on delay in pwm mode delay bits switch-on delay 000 no delay 001 32 pwm clock periods 010 64 pwm clock periods 011 96 pwm clock periods 100 128 pwm clock periods 101 160 pwm clock periods 110 192 pwm clock periods 111 224 pwm clock periods external clock & inte rnal pwm (clock_int_s = 0) the channels can be controlled by an external clock signal b y setting bit d6 =0 of the ocr_ s register (clock_int_s). duty cycle values specified in table 6 apply. when an external clock is used, the value of frequency division (256 when pr[x] = 0) may be doubled by setting the prescaler bit pr[x]) = 1(bit d7 of the ocr_s reg.). this a llows driving the channels at different switching frequencies from a single clock signal. simultaneously setting pwm_en_1=1 and pwm_en_0=1 will synchronize the channels. the clock frequency on the clock pin is monitored when externa l clock (clock_int_s = 0) and pulse width modu lation (pwm_en_s = 1) are both selected. if a clock failu re occurs under these conditions (f< f clock(low) or f> f clock(high) ), the external clock signal will be ignored and a fault is detected (fsb =0, clock_fail bit is set (od2 in the diagr register). the state of t he on_s bit in the spi register then determines the channel?s s witching state. to return to external clock mode (and reset fsb), the clock-fail bit must be read and the external clock has to be within the authorized range again. internal clock & internal pwm (clock_int_s bit = 1) by using a reference time slot (usually available from an externa l microcontroller), the period of each of the internal pwm clocks can be changed or calibrated (see programmable pwm module ). calibration of the default period = 1/f pwm(0) reduces its maximum variation from about +/-30% to +/- 10%. the programming procedure is initialized by sending a dedicated word to the si-calr register (see table 11 ). next, the device sets the new value of the switching period in 2 steps. firs t it measures the time elapsed between the first falling edge on the csb pin and the next rising edge on the csb pin (t csb ). then it changes the value
analog integrated circuit device data ? freescale semiconductor 31 06XS4200 functional device operation operation and operating modes of the internal clock period accordingly. the actual value of the channel?s switching period is obtained by multiplying the internal clock period by 256. csb si calr_s si command ignored internal clock period of channel s t csb t csb when the duration of the negative csb pulse is outside a predefined time slot (from t csb(min) to t csb(max) ), the calibration event will be ignored and the internal clock frequency will remain unchanged. if the value (f pwm(0) ) has not been previously calibrated, it will remain at its default level. synchronization of both channels when internal clock signals are used to drive the pwm modul es, perfect synchronization over a long time can not be achieved since both clock signals are independent. however, when the channels are driven from an external clock, perfect synchronization can be achieved by simultaneously setting pwm_en_1=1 and pwm_en_0=1. the best way to optimize emc is to use an external clock with a staggered switch on delay (see table 7 ). parallel operation the channels can be paralleled to drive higher currents. setting the parallel bit in the gcr register to logic [1] is mandatory in this case. the improved synchronization of both transistors will allow an equal current distribution between both channels. in pa rallel mode, both output pins (hs[x]) must be connected (as well as both in[x] pins in case of external control). conf0 and conf1 must be set to equal values. 1- device configuration in parallel mode: there are two ways to config ure th e on/off control: spi- configured pwm control and direct input control. ? spi config ured parallel mode : the switching configuration is solely defined by the (si) pwmr_0 , confr_0, ocr_0, and retry_0 registers. as soon as parallel=1, the contents of the corresponding registers in bank 1 will be replac ed by that of bank 0, except bits d6-d8 of the confr_1 re gister (configuration of the open load/output short-circuite d diagnostics). after setting parallel=1, contents of so registers in bank 0 are copied to registers of bank 1 only when new information is written in them. bits od3, od4, and od 5 of both faultr_s registers (olon, oloff, os) are always reported independently. ? dire ct input controlled parallel mode: the in0 and in1 pins must be connected externally. 2- diagnostics in parallel mode: the diagnostics in parallel mode operate as follows: ? open-load in off state and - op en-load in on state: the ol_on and ol_off bits of both faultr registers wil l independently report failures of the channels according to the settings of bits d7 and d6 of the confr_s register. ? current sensing: refer to the table 22 for a description of the various current sensing modes. only the current sense ratio of bank 0 (d5 of the ocr_0 register) is considered. the corresponding bit in the ocr_1 register is copied from t hat of the ocr_0 register. ? output shorted to battery: the os-bit (od3) of each of both fault registers will in dependently report this fault, according to the settings of bit d8 of the confr_s reg. 3- protections in parall el mode: ? over-current: -only the configuration of over-current thresholds & bl anking windows of channel 0 are considered. -in case over-current (oc) occurs on any channel, both chan nels are turned-off. regardless the order of occurrence of overcurrent (oc), both oc-bits (od0) in the fault registers are simultaneously set to logic 1. ? severe short-circuit: in case of sc detection on any channel, both channels are turned -off and the sc bits (od1) in both fault registers are simultaneously set to logic 1. ? over-temperature: in case of ot detection on any channel, both channels are turned -off and both ot bits in the fault registers (od2) are simultaneously set to logic 1. ? auto-retry: only one 4-bit auto-retry count er specifies the number of successive turn-on events on paralleled channels (retryr_0). the counter value in register retryr_1 (od4?od7) is copied from that in retryr_0. to delatch the channels, only channel 0 needs to be de latched.
analog integrated circuit device data ? 32 freescale semiconductor 06XS4200 functional device operation operation and operating modes protection and diagnostic features protective functions over-temperature faul t (latchable fault) the channels have individual over-temperature detection. as soon as a channel?s junction temperature rises above t sd (175 c typ.), it is turned off, the over-temperature bit (ot = od2) is set, and fsb = 0. fsb can only be reset by tu rning on the channel when the junction temperature of both channels has dropped below the threshold: t j 50 kohms or vih (2.0 v)< v(conf) < 5.0 v inductive: conf = 1, dc motor mode when over-current windows are active, current sensing is disabled and the syncb pin remains high. this is illustrated by figure 13 . after turn on, the output voltage (second waveform (20 v/div.) and the output cu rr ent (first waveform, 12 a/div.) rise immediately, but the current sense voltage (third waveform, 2.0 v/div, 1.0 v = 3.0 a) and its synchronization signal sy nc (fourth waveform, 5.0 v/div.) on ly become active at the end of the selected over-current window (duration t ocm2_l ). figure 13. current sense blanking during over-current wi ndow activity activation of the lighting profile is time driven and activation of the dc motor profile is event driven, as explained below. in lighting mode, the height of th e over-current profile is defined by three different thresholds (i _och , i _ocm and i _ocl , which stands for the higher, the middle, and the lower over- current threshold), as illustrated by figure 5 . this profile has two adjacent windows the width of which is compatible with typical bulb inrush current profiles. the width of the first of these windows is either t och1 or t och2 . the width of the second windows is either t ocm1_l or t ocm2_l (see table 17 ). the lighting profile is activated at each turn-on event in cluding auto-retry, except in switch mode. in switch mode, the profile is activated only at the first turn-on event, but is not renewed. during the on-period, the load current is continuously compared to the programmed over-current
analog integrated circuit device data ? freescale semiconductor 33 06XS4200 functional device operation operation and operating modes profile. the channel is switched off when a threshold is crossed or a window width is exceeded. in dc motor mode, only one over-current wind ow exists, defined by only two different thresholds (i _och and i _ocl) as illustrated by figure 6 . this window is opened anytime the output current exceeds the selected lower over-current th reshold (i oclx ). in this case, the allowed over-current duration is defined by parameters t ocm1_m , t ocm2_m , t och1 , and t och2 . the selection of the different profiles and values is expl ained in the section address a0100 ? over-current protection configuration register (ocr_s) . auto-retry after over-current shut off when auto-retry is activa ted, oc-latching ( over-current fault (latchable fault) ) only occurs after expiration of the available amount of auto-retries (described in section auto- retry ). switch mode operation and over-current duration switch mode is defined as a ny device operation with a duty cycle lower than 100% at a frequency above f pwm_ext (min.) or f pwm_int (min.). the device may operate in switch mode in internal/external pwm or in direct input mode. in switch mode, the accumulated time spent by the load current in a particular window segm ent during on-times of successive switching periods is identified by the aforementioned duration counter, and compared to the active segment width. the associated off-times are excluded by the duration counter. the channel is turned-off when the value of the counter exceeds the window width. in figure 14 , over- current detection shutdown is s hown in cas e of switch mode operation with a duty cycle of 50% (solid line) and 100% (fully-on, dashed line). the device is turned off much later in switch mode than in fully-on mode, since the duration counter only counts over-current during on-times. figure 14. over-current shutdown in pwm mode (solid lin e) and fully-on mode (dashed line) reset of the duration counter reset of the duration counter is achieved by performing a de latch sequence ( fault delatching ). in lighting mode (confs = 0), this counter is also reset automatically at each au to-retry (but not in dc motor mode). in dc motor mode, the duration counter is reset either by pe rforming a delatch sequenc e or (automatically) after occurrence of a new on-period without any over-current ([hson[x]=1). reset then actually occurs at the first turn-off instant following that on-period. in switch mode, the duration co unter is not reset by normal pwm activity unless delatching is performed. severe short-circuit fault (latchable fault) when a severe short-circuit (sc) is detected at turn-on (wirin g length l load < l short , see table 3 ), the channel is shut off immediately. for wiring lengths above l short , the device is protected from short- circuits by the normal over- current protection functions ( over-current fault (latchable fault) ). when an sc occurs, fsb goes low (logic [0]), and the sc bit is set, eventually followed by an auto-retry. sc is of the la tchable fault type (see protection and diagnostic features and fault delatching ). over-voltage detection (en abled by default) by default, the supply over-voltage protection (v pwr ) is enabled when over-voltage occurs (v pwr > v pwr(ov) ), the device will turn off both channels simultaneously, the fsb pin is asserted low, and the ov fault bit is set to logic [1]. the channels remain off until the supply voltage drops below a threshold voltage v pwr < v pwr(ov) - v pwr(ovhys) . the ov bit can then be reset by reading out the statr register. the over-voltage protection can be disabled by setting the ov _dis = 1 in the general configuration (gcr) register. in this case, the fsb pin will neither assert a fault occurrence, nor will the channels be turned off. however, the fault register (ov bit) will still report an over-voltage occurrence (when v pwr > v pwr(ov) ) as a warning. when v pwr > v pwr(ov) , the value of the on-resistance on both channels (r ds(on ) ) still lays within the ranges specified in table 3 . under-voltage fault (latchable fault) the channels will always be turned off when the supply voltag e (v pwr ) drops below v pwr(uv) . fsb drops to logic [0], and the fault register?s (co mmon) uv bit is set to [1]. when the under-voltage condition then disappears, two di fferent cases exist: ? if the channel?s internal control signal hson[x] is off, fsb wil l return to logic [1], but the uv bit will remain set until at least one output is turned on (warning). ? if the channel?s control signal is on, the channel will only be turned on if a delatch or por sequence is performed prior to the turn on request. the uv bit can then only be reset by reading out the statr register. auto-retry (if enabled) will start as soon as the uv cond ition disappears.
analog integrated circuit device data ? 34 freescale semiconductor 06XS4200 functional device operation operation and operating modes extended mode protection in extended mode (6.0 v < v pwr < 8.0 v or 36 v < v pwr < 58 v), the channels are still fa u lt protected, but compliance with the specified protection levels is not guaranteed. the register settings however (i ncluding previously detected faults) remain unaltered, provided v dd is within the authorized range. below 6.0 v, the channels are only protected from over-temperature, and this fault will only be reported in the spi regi ster at the moment v pwr has again risen above vpwr (uv) . to allow the outputs to remain on between 36 and 58 v, over-voltage detection should be disa bled (by setting ov_dis = 1 in the gcr register). faults (over-temperature, ov er-current, severe short- circuit, over and under-voltage) are reset if: ?v dd < v dd(fail) with v pwr in the normal voltage range ?v dd and v pwr are below the v supply(por) voltage threshold ? the corresponding spi regi ster i s read after the disappearance of the failure cause (and delatching) drain/source over-voltage protection the device will try to limit t he drai n-to-source voltage by turning on the channel whenever v ds exceeds v ds(clamp) . when a fault occurs (sc, oc, ot, uv), the device is rapidly switched off (in t < t fault s), regardless the value of the selected slew rate. this may induce voltage surges on v pwr and/or the output pin (hs[x]) when connected to an inductive line/load. turning on the device also dissipates the energy stored in the inductive supply line. this function monitors over-voltage for v pwr > 30 v. for supply voltages v pwr < 30 v, the device will be prot ecte d from negative output voltages by automatically turnin g on the channel. the feature remains functional after device ground loss. supply over-voltage protection in order to protect the device from excessive voltages on th e supply lines, the voltage between the device?s supply pins (vpwr and the gnd) is monitored. when the v pwr -to-gnd voltage exceeds the threshold v d_gnd(clamp) , the channel is automatically turned on. the fe ature is not operational in cases of ground loss. negative output voltage protection the device will try to limit the under-voltage on the output pin s hs[x] when turning off inductive loads. when the output voltage drops below v cl , the channel is switched on automatically. this fe ature is not guaranteed after a device ground loss. the energy dissipation capabilities of the circuit are defin ed by the e cl [0:1] parameters. for inductive loads larger than 20 h, it is recommended to employ a freewheeling dio de. the three different over -voltage protection circuits are symbolically represented in figure 15 . the values of the clamping diodes are those specified in table 3 . coupling factor k represents the current ratio between the current in the supply voltage measurement diode (zener) and the current injected into the mosfet?s gate to turn it on. . imeg gnd loa d hs[ x] dc v ds(clam p)- v th v d_gnd (clamp) i 2 v cl- v th k.i z v th figure 15. supply and output voltag e protections reverse voltage protection on v pwr the device can withstand reverse supply voltages on v pwr down to -28 v. under these condit ions, th e outputs are automatically turned on and the channel?s on-resistance (r ds(on) ) is similar to that during positive supply voltages. no additional components are required to protect the v pwr circuit except series resistors (>8.0 k) between the direct inputs in[0:1] and v pwr in case they are connected to vpwr. the vdd pin needs reverse voltage protection from an externally connected diode ( figure 21). load and system ground loss in case of lo ad ground loss, the channel?s state will not change, but the device will detect an open-load fault. in case of a system gnd loss, the channels will be turned off. device ground loss in the (improbable) case the device loses all of its three grou nd connections (pins 14, 17, and 22), the channels? state (on/ off), will depend on several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device?s momentary current consumption (influenced by the spi settings) and the state of other high side switches on th e board when there are pins in common like fsb, fsob and sync. in the below description, all voltages ar e referenced to the system (module) gnd. when series resistors are us ed, the ch annel state can be controlled by entering fail-saf e mode. the channels will be turned off automatically when the voltage applied to the in[x] input(s) through the series resistor(s) is not higher than v dd and be turned on when the in[x] input(s) are tied to v pwr . fail-safe will be entered under the following conditions: ? all unused pins are tied to the overall system?s gnd conn ection by resistors > 8.0 k.
analog integrated circuit device data freescale semiconductor 35 06XS4200 functional device operation operation and operating modes ? any device pin connected to external system components has a series resistors > 8.0 k (except pins v pwr , v dd , hs[0], hs[1] and r(csns)>2.0 k) ? pins fsb, fsob and sync are in the logic high state when they are shared with other devices. this means that none of the other devices is in fault or fail-safe mode, nor should current sensing be performed on any one of them when gnd is lost when no series resistors are employed, the channel state after gnd loss will be determined by the voltage on pins in[0:1] and the voltage shift of the device gnd. device gnd shift is determined by the lowest value of the external voltage applied to either pin of the following list: clock, fsb, in[0:1], fsob, sclk, cs,si, so, rstb, conf[0:1], sync, csns. when the device gnd voltage becomes logic low (v(gnd)< v il ), the spi port will cont inue to operate and the device will operate normally. when the gnd voltage becomes logic high (v(gnd)> v ih ), spi communication will be lost and fail-safe mode wil l be entered. when the voltage applied to the in[0:1] input is v pwr , the channel will be turned on: when it is v dd , the channel will be turned off if (v dd - v(gnd)) < v ih . supply voltages out of range v dd out of range if the external v dd supply voltage is lost (or falls outside the authorized range: v dd v pwr (por) , after a period v pwr < v pwr (por) (and v dd < v dd (por) before and after) 2. v dd > v dd (por) after a period with v dd < v dd (por) (v pwr < v pwr (por) before and after) por is also set at the transition to wake-up (by setting rstb=1 or in[x]=1) when v pwr > v pwr (por) (before and after) or v dd >v dd(por) (before and after). por is not performed when v pwr > v pwr (por) after a period v pwr < v pwr (por) (and v dd > v dd (por) permanently).
off on latched off off on (ov = 1) (fc[x] = 1 and (ov = 0)) (fc[x]= 0 or ov = 1) (fc[x] = 0) (fc[x] = 0) (fc[x] = 0) (retry = 1) = > count = count+1 (retry = 1) (count = 16) (after retry period and ov = 0 and ot = 0 and uv = 0) (open-loadoff = 1 or os = 1 (open-loadoff = 1 or os = 1 (openloadoff = 1 or os = 1 (open-loadon = 1) (open-loadon = 1) or ov = 1) or ov = 1 or ov = 1) or uv = 1 or ot = 1) auto-retry loop analog integrated circuit device data ? 36 freescale semiconductor 06XS4200 functional device operation operation and operating modes figure 16. state machine: fault occurrence and auto-retry auto-retry the auto-retry circuitry will autom atically try to turn on the channel on a cyclic basis. only faults of the latchable type (over-current, severe short-circuit, over-temperature (ot), and under-voltage (uv)) may activate auto-retry. for uv and ot faults, auto-retry will only start after disappearance of the failure cause (when auto-retry is enabled). the retry condition is expressed by: retry[x] = oc[x] or sc[x] or ot[x] or uv. if auto-retry has been enabled, its mode of operation will dep end on the settings of the auto-retry related bits (bits d0...d3 of the si-retry_s register, see table 11 ) and the available amount of auto-retrie s (bits od7...od4 of the so- retry_s reg.). more details can be found in amount of auto-retries . if auto-retry was disabled, latchable faults will immediately be la tched upon their occurrence (see protection and diagnostic features ). auto-retry configuration to enable the auto-retry function , bit retry_s (d0 of the si retry_s register) has to be set to the appropriate value. auto-retry is enabled for retry_s = 0 when the channel is configu red for lighting applications (conf=0). it is enabled for retry_s=1 for dc motor applications (conf[x] =1). table 9. auto-retry activation for lamps (conf=0) and dc motors (conf=1) conf[x] retry_s bit auto-retry 0 0 enabled 0 1 disabled 1 0 disabled 1 1 enabled if auto-retry is enabled, an auto-retry sequence will start when the channel?s fault control signal is set to 1 (fc[x] = 1, see fault delatching ) and the retry condition applies (retry[x]=1, see auto-retry ). when a failure occurs (fault = 1), the channel will au tomatically be switched on again after the auto-retry period. the value of this period (t auto ) is set through the spi port (bits d2 and d3 of the retry_s register, see table 21). when the failure cause disappears before expiration of the avai lable amount of auto-retries, the device will behave normally (fsb = 1), but the retry counter keeps its current valu e and the fault bit remains set until it is cleared. this guarantees a maximum device ava ilability without preventing fault detection.
analog integrated circuit device data freescale semiconductor 37 06XS4200 functional device operation operation and operating modes amount of auto-retries in case the device was configured for an unlimited amount of auto-retries (retry_unlimited_s = 1), auto-retry will continue as long as the device remains powered. the channel will never be latched off. in case a limited amount of retries was selected (retry- unlimited_s = 0), auto-retry will continue as long as the value of the 4-bit auto-retry counter does not exceed 15 (bits od4...od7 of the retry_s register). after 15 retries, the rfull bit of the statr (od4 for channel 0, od5 for channel 1) register will be set to logic high. the amount of available auto-retries is then reduced to one. if the fault still hasn?t disappeared at the next retry, the corresponding channel will be switched off definitively and the fault is latched (fsb = 0, see protection and diagnostic features and fault delatching ). any channel can be turned on at any moment during the auto-retry cycle by performing a delatch sequence. however, this will not reset the retry counter. the value of the auto-retry counter can be read back in normal mode only (so-retryr register bits od7-od4). reset of the auto-retry counter any one of the below events will reset the retry counter: ? fail-safe is entered ( fail-safe mode ) ? sleep mode is left ( sleep mode ) ? por occurs ( supply voltages out of range ) ? the retry function is set to unlimited (bit retry- unlimited_s = 1 (d1 = 1)) ? the retry function is disabled (retry_s bit= d0 of the retry_s register under goes a 1-0 transition for conf = 1 and a 0-1 transition for conf = 0). if the channel was latched at the moment the auto-retry counter was reset (case 4), the channel will be delatched, and be turned on after one retry period (if retry was enabled). auto-retry and over -current duration during the on-period following an auto-retry, the load current profile will be compared to the length and height of the selected over-current threshold profile, as described in the section on over-current protection (see over-current fault (latchable fault) ). when the lighting profile is activated, the over-current duration counter is reset at each auto-retry (to allow sustaining new inrush currents). for dc motor mode however, it is only reset at the turn-off event of the first pwm period wit hout any over-current (see reset of the duration counter ). figure 16 gives a description of the retry state machine with the various transitions between operating modes. diagnostic features diagnostic functions open-load-in-on state (olon), open- load-in-off-state (oloff) and output short-circuited to v pwr (os) are operational over the frequency and duty cycle ranges specified in table 4 . occurrence of an olon, olof f, or os fault will set the associated bit in the faultr_s register but will not trigger automatic turn-off. any of these diagnostic functions can be disabled by setting olon_dis_s=1, oloff_dis_s=1, or os_dis_s=1 (bits d8...d6 of the confr reg.). the functions are guaranteed ov er the specified ranges for output capacitor values up to 22 nf (+/-20%). output shorted-to-v pwr fault the device will detect short-ci rcuits between the output and v pwr . the detection is performed during the off-state. the output-shorted-to-v pwr fault-bit (os_s) is set whenever the output voltage rises above v osd(thres) . the fault is reported in real time on the fsb pin and saved by the os_s bit. occurrence of this fault wi ll not trigger automatic turn-off. even if the short-circuit disappears, the os_s bit will not be cleared until the faultr register is read. the function may be disabled by setting os_d is_s=1. the function will operate over the duty cycle ranges specified in diagnostic features . this type of event shall be limited to 1000 min during the vehicle lifetime. in case of pe rmanent output shorted to the battery condition, it is needed to turn-on the corresponding channel. open-load detection in off state open-load-in-off-state detect ion (ol_off) is performed continuously during each off-state (both for csr0 and csr1). this function is impl emented by injecting a small current into the load (i old(off) ). when the load is disconnected, the output voltage will rise above v old(thres) . ol_off is then detected and the ol_off bit in the faultr register is set. if disappearance of the open load fault is detected, the fsb output pin will re turn to a high immediately, but the ol_off bit in the fault register will remain set until it is cleared by a read out of the faultr register. the function may be disabled by setting oloff_dis_s=1. the function will operate over the duty cycle ra nges specified in section diagnostic features . open-load detection in on state (ol_on) open-load-in-on state detection (olon) is performed continuously during the on-state for csr0 over the ranges specified in section diagnostic features . an open-load in on state fault is detected when the load current is lower than the open-load current threshold i old(on) . this will happen at i old(on) = 500 ma (typ.) for high current sense mode (csr0), and at 7.0 ma (typ.) for low current mode. fsb is asserted low and the olon bit in the fault register is set to 1 but the channel remains on. fsb will go high as soon as disappearance of the failure cause is detected, but the ol_on bit remains set. in high current mode (csr0), open-load in on state detection is done continuously during the on-state and the olon-bit remains set even if the fault disappears.
analog integrated circuit device data 38 freescale semiconductor 06XS4200 functional device operation operation and operating modes in high current mode, the olon-bit is cleared when the faultr register is read during the off state, even if the fault hasn't disappeared. the olon bit is also cleared when the faultr register is read during the on state, provided the failure cause (load disconnected) has disappeared. in low current mode (csr1), ol_on is done periodically instead of continuously and only o perates when fast slew rate is selected. when the internal pwm module is used with an internal or external clock (case 1), the period is 150 ms (typ.). when the direct inputs are used (case 2), the period is that of the input signal. the detection instants in both cases are given by the following: 1. in internal pwm (int./ext. clock) , low current mode (csr1) , open-load-in-on state detection is not performed each switching period, but at a fixed frequency of about 7.0 hz (each t olled =150 ms typ.). the function is available for a duty cycle of 100%. olon detection is also performed at 7.0 hz, at the first turn-off event occurring 150 ms after the previous ol_on detection event (before os and ol_off). 2. in direct input , low current mode (csr1) , ol_on is performed each switching period (at the turn-off instant) but the duty cycle is restricted to the values. consequently, when the signal on the in[x] pin has a duty cycle of 100%, ol_on will not be performed. to solve this problem, either the internal pwm function must be activated with a duty cycle of 100%, or the channel?s direct input must be disabled by setting dir_dis_s=1 (bit d5 of th e confr-s register). the olon-bit is only reset when the faultr register is read after occurrence of an ol_on-detection event without fault presence. open-load detection in discontinuous conduction mode if small inductive loads (solenoids / dc motors) are driven at lower frequencies, disc ontinuous conduction mode may occur. undesired open-load in on state errors may then be detected, as the inductor current needs some time to rise above the open-load detection threshold after turn-on. this problem can be solved by increasing the switching frequency or by disabling the function a nd activating open-load in off state detection instead. when small dc motors are driven in discontinuous conduction mode, undesired open-load in off state detection may also occur when the load current reaches 0 a during the off state. this problem can be solved by increasing the switching frequency or by enabling open-load in off state detection only during a limited time, preferably directly after turn-off (see diagnostic features ). the signal on the sync pin can be used to identify the turn-off instant. current & temperature sensing the scaled values of either of the output currents or the temperature of the device?s gnd pin (#14) can be made available at the csns pin. to monitor the current of a particular channel or the general device temperature, the csns0_en and csns1_en bits in the general configuration register (gcr) must be set to the appropriate values. when over-current windows are active, current sensing is disabled and the syncb pin remains high. instantaneous and sampled current sensing the device offers two possibilit ies for load current sensing: instantaneous (synchronous) sensing mode and track & hold mode (see figure 8 ). in synchronous mode, the load current is mirrored through the current sense pin ( output current monitoring (csns) ) and is therefore synchronous with it. after turn-off, the current se nse pin does not output the channel current. in track & hold mode however, the current sense pin continues to mirror the load current as it was just before turn-off. synchronous mode is activated by setting the t_h_en bit to 0, and track & hold mode by setting the t_h_en bit to 1. current sense ratio selection the load current is mirrored through the csns pin with a sense ratio ( figure 17 ) selected by the csns_ratio bit in the ocr register. to achieve optimal accuracy at low current levels, the lower current sensing ratio, called csr1, must be selected. in that case, the over-current threshold levels are decreased. the best accuracy that can be obtained for either ratio is shown in figure 18 . the amount of current the csns pin can sink is limited to i csns,max. .the csns pin must be connected to a pull-down resistor (470 : < r(csns) <10 k : , 1.0 k : typical), in order to generate a voltage output. a small low-pass filter can be used for filtering out switching transients ( figure 21 ). current sensing will operate for load currents up to the lower over-current threshold (oclx a). synchronous current sensing mode for activation of synchronous mode, t_h_en must be set to 0 (default). after turn-on, the csns output current will accurately reflect the value of the channel?s load current after the required settling time. from this moment on (csns valid), the sync pin will go low and remain low until a switch off signal (internal/external) is received. this allows synchronization of the device?s current sensing feature with an external process running on a separate device (see current sense synchronization (sync) ). after turn-off, the load current will not flow through the switch, and the load current cannot be monitored. track & hold current sensing mode in track & hold mode (t&h) (t_h_en = 1), conversely from synchronous mode, the csns output current is available even after having switc hed off the load. this feature is useful when the device oper ates autonomously (internal clock/pwm), since it allows current monitoring without any synchronization of the device. an external sample and hold (s/h) capacitor is not requir ed. after turn on, the csns output current reflects the channel?s load current with the specified accuracy after occurr ence of the negative edge on the sync pin, as in synchronous mode (see current sense synchronization (sync) ). however, at the switch-off instant,
analog integrated circuit device data ? freescale semiconductor 39 06XS4200 functional device operation operation and operating modes the last observed csns current is sampled and its value saved, thanks to an internal s/h capacitor. the sync pin will go high (sync = 1). if the channel on which track & hold current se nsing is performed is changed to another, the internal s/h hold capacitor is first emptied and then charged again to allow current monitoring of the other channel. consequently, t&h current monitoring of a channel is lost when this channel is in the off state at the moment the current is monitored on the other channel. track & hold mode should not be used for frequencies below 60 hz. . figure 17. current sensing ratio versus output current current sense errors current sense accuracy is adversely affected by errors of t he internal circuitry?s current sense ratio and offset. the value of the current sensing out put current can be expressed with sufficient accuracy by the following equation: i csns = (i(hs[x])+ i _load_err_sys + i _load_err_rand )*c srx (1) with c sr0 = (1/5000+ ? gain0 ) and c sr1 = (1/ 166 6.6+? gain1 ). the device?s offset error has a ?system atic? and a ?random? component (i _load_err_sys , i _load_err_rand ). at low current levels, the random offset error may become dominant. the systematic offs et error is caused by predictable variations with supply voltage and temperature, and has a small but positive value with small spread. the random offset error is a randomly distributed parameter with an average value of zero, but with high spread. the random offset error is subject to part-to-part variations and also depends on the values of supply voltage and device temperature. the device has a special feature called offset compensation, allowing an almost comp lete compensation of the random offset error (see e sr0_err ). this offset compensation technique greatly minimizes this error. compu ting the compensated current sensing value is illustrated in th e next sections. activation and use of offset compensation according to the settings of the ofp_s bit (in the retr yr_s register), opposite va lues of the random offset error are generated. to compensa te the random offset error, two separate measurements with opposite values of the random offset error are require d. the measured values must be saved by an external -processor. compensation of the random offset error is achieved by computing the average of both. when a dedicated bit called offset positive (ofp = bit d 8 of the retryr_s register) is set to 1, the current sunk through the csns pin (i csns ) can be described by: i csns1 =csr x *(i load + i _load_err_sys + i _load_err_rand )( 2 ) when bit ofp is set to 0, i csns can be described by: i csns2 = csr x *(i load + i _load_err_sys - i _load_err_rand ) (3) the random offset term i _load_err_rand can be computed from equations (2) and (3) as follows: i _load_err_rand = (i csns1 - i csns2 ) / (2*csr x )(4) the compensated current sense value i csns,comp can be obtained by computing the average value of measurements i csns1 and i csns2 as follows: i csns,comp = (i csns1 + i csns2 ) / 2 (5) when equations 2 and 3 are substituted in equation 5, the rand om offset error cancels out, as shows eq. 6: i csns,comp = (i _load_err_sys + i load ) * csr x (6) the systematic offset error i _load_err_sys is referenced at the operating point 28 v and 25 c. it can eventually be fine tune d by performing a calibration. gain errors at 25 c (=cu rrent sense ratio errors, represented by ? gain0 and ? gain1 ) can also be reduced by performing a calibration at a point in the range of interest. if calibration can not be done, it is recommended to use the typical value of i _load_err_sys (see e sr0_err ). current sense error model the figures of uncompensated and compensated current sense ac curacy mentioned in table 3 have been obtained applying the error model of eq. 7 to the data: i csns_model = (i(hs[x])+ i _load_err_sys ) * c srx (7) e srx_err = (i csns1 - i csns_model )/i csns_model (8) e srx_err(comp) = (i csns,comp - i csns_model )/ i csns_model (9) the computation has been applied to each of the specified measu rement points. model parameters i _load_err_sys and c srx have the nominal values, specified in e sr0_err . the load current can be computed from this model as: i(hs[x]) = i csns / csr x - i _load_err_sys (10) i(hs[x]) = i csns,comp / csr x - i _load_err_sys (11)
analog integrated circuit device data ? 40 freescale semiconductor 06XS4200 functional device operation logic commands and spi registers using expression (11) generally gives more accurate values than expression (10), since in expression (11), random offset errors have been compensated. offset compensation in track & hold mode in track & hold mode, the last observed sense current (i csns ) is sampled at the switch off instant. this takes into account the currently active se ttings of the ofp_s offset compensation bit. changing the value of the ofp bit during the switch?s off time will prod uce an identical value of the current sense output. consequentl y, to implement the before mentioned offset compensation technique, the channel must have been turned on at least once prior to sensing the output current with an opposite value of the ofp bit. system requirements for current monitoring current monitoring is usually implemented by reading the (rc-filtered) vo ltage across the pull-down resistor connected between the csns pin and gnd ( figure 21 ). therefore, measurements (1) and (2) must be spaced sufficiently wide apa rt (e.g. 5 time constants) to get stabilized values, but close enough to be sure that th e offset value wasn?t changed. the a/d converter of the external micro controller that is used to read the current sense voltage v(csns) must have sufficient resolution to avoid introducing additional errors. accuracy with and without offset compensation the sensing accuracy for csr0 and csr1, obtained before an d after offset compensation, is shown in figure 18. . figure 18. current sense accuracy versus output cu rrent in track & hold mode, the accuracy of the current sense fu nction will be lowered according to the values shown in figure 19 (error percentage as a function of the switch-off time is displayed, for csr0 and csr1). track & hold mode shou ldn?t be used below f= 60 hz. figure 19. track and hold current sense accuracy temperature prewarning detection in normal mode, the temperature prewarning (otw) bit is set (b it od8 of the faultr register), when the observed temperature of the gnd pin is higher than t otwar (pin #14, see figure 3 ). the feature is useful when the temperature of the direct surroundings of the de vice must be monitored. to be able to reset the otw-bit, the faultr register must be read after the moment that temperature t c < t otwar . switching state monitoring the switching state (on/off) of the channels is reported in real time by bits out[x] in the statr register (bit od0/od1). the out[x] bit is asserted logic high when the channel is on (output voltage v(hs[x ]) higher than v pwr /2). when supply voltage v pwr drops below 13 v, the reported switching state may not correspond to the state of the channel?s control signal hson[x] in case of an open load fault (see factors determining the channel?s switching state ). emc performances specified emc performance is board and module dependent and applies to a typical application ( figure 21). the device withstands transients per iso 7637-2 /24 v. an externa l freewheeling diode connected to at least one output is required for sustaining iso 7637-2 pulse 1 (-600 v). to withstand pulse 2, at least one of the two channels must be connected to a typical load (bul b). it withstands electric fields up to 200 v/m and bulk current injection (bci) up to 200 ma pe r iso11452. the device meets class 5 of the cispr25 emission standard. logic commands and spi registers spi protocol description the spi interface offers full duplex, synchronous data transfer over four i/o lines: se rial input (si), serial output (so), serial clock (sclk), and chip select ( csb ).the si / so pin s of the device follow a first-in first-out (d15 to d0) protocol. transfer of input a nd output words st arts with the most significant bit (msb). al l inputs are compatible with 5.0 v or 3.3 v cmos logic levels. parity check is performed after tra nsfer of each 16-bit spi data word.the spi interface can be driven without series re sistors provided that voltage
analog integrated circuit device data ? freescale semiconductor 41 06XS4200 functional device operation logic commands and spi registers ratings on vdd and spi pins ( table 2 ) aren?t exceeded. unused spi-pins must be tied to gnd, eventually by resistors (see device ground loss ). 1. rst must be in a logic [1] state during data transfer. 2. data enter the si pin starting with d15 (msb) and ending with bit d0. 3. data are available on the so pin starting with bit 0d15 (msb) and ending with bit 0 (od0). notes 1. rstb must be in a logic [1] state during data transfer. 2. data enter the si pin starting with d15 (msb) and ending with bit d0. 3. data are available on the so pin starting with bit 0d15 (msb) and ending with bit 0 (od0). notes csb sclk si so d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 figure 20. 16-bit spi interface timing diagram serial input communication protocol spi communication requires that rstb = high. spi communication is accomplis hed with 16-bit messages. a valid message must start with the msb (d15) and end with the lsb (d0) ( table 10 ). incoming messages will be interpreted according to table 11 . the msb, d15, is the watchdog bit (wdin). bit d14, parity check (p), must be set such th at the total number of 1-bits in the spi word is even (p=0 for an even number of 1-bits and p=1 for an odd number). bank selection is done by setting bit d13. bits d12 : d10 are used for register addressing. the remaining ten bits, d9 : d0, are used to configur e th e device and activate diagnostic and protective functions. multiple messages can be transmitted for applications with daisy chaining (or to validate already transmitted data) by keeping the csb pin at logic 0. messages with a length different from a multiple of 16 or with a parity error will be ignored. the device has thirteen input registers for device configuration and thirteen output registers containing the faul t/device status and settings. table 11 gives the si register function assignment. bit names with extension ?_s? refer to functions that have been imple mented independently fo r each of both channels. serial port operation when chip select occurs (1-to-0 transition on the csb pin), the output register data is clocked out of the so pin (msb-first) at the serial clock frequency (slck). bits at the si pin are clocked in at the same time. the first sixteen so register bits are those addressed by the previous si word (bit d13, d2?d0 of the statr_s input register). at the end of the chip select event (0-to-1 transition), the si register contents are latched. the seco nd spi word clocked out of the serial output (so) after the first csb event represents the initial so register contents. this allows daisy chaining and data integrity verification. the message length is validated at the end of the csb event (0-to-1 transition). if it is valid (multiples of 16, no parity error), the data is latched into the selected register. after latch-in, the so pin is tri-stat ed and the status register is updated with the latest fa ult status information. daisy chain operation daisy-chaining propagates commands through devices conn ected in series. the commands enter the device at the si pin and leave it by the so pin, delayed by one command cycle of 16 bits. to address a particular device in a daisy chain, the csb pin of all the devices in that chain has to be kept low until the spi message has arrived at its destination. once the command has been clocked in by the addressed device, it can be executed by setting csb=1.
table 10. si message bit assignment bit n si reg. bit bit functional description msb . . . . lsb d15 watchdog in (wdin): its state must be alter nated at least once within the timeout period d14 parity (p) check. p-bit must be set to 0 for an even number of 1-bits and to 1 for an odd number. d13 selection between si registers from bank 0 (0= channel 0) and bank 1 ( table ). d12 : d10 register address bits. d9:d0 used to configure the device and the protective functions and to address the so registers. table 11. serial input register addresses and function assignment si register si data d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 statr_s wdin p a 0 0 0 0 0 0 0 0 0 0 0 soa2 soa1 soa0 pwmr_s wdin p a 0 0 0 1 0 on_s pwm7_s pwm6_s pwm5_s pwm4_ s pwm3_s pwm2_s pwm1_s pwm0_s confr_s wdin p a 0 0 1 0 0 os_dis_s olon_dis _s oloff_dis _s dir_dis_s sr1_s sr0_s delay2_s delay1_s delay0_ s ocr_s wdin p a 0 1 0 0 0 hocr_s pr_s clock_int_s csns_rati o_s t och_s tocm_s och_s ocm_s ocl_s retry_s wdin p a 0 1 0 1 0 ofp_s 0 0 0 0 auto_period 1_s auto_period 0_s retry_unli mite d_s retry_s gcr wdin p 0 1 1 0 0 pwm_en _1 pwm_en_ 0 parallel t_h_en wd_dis v dd_fail_en csns1_en csns0_en ov_dis calr_s wdin p a 0 1 1 1 0 1 0 1 0 1 1 0 1 1 contents a fter reset* 0 x 0 x x x 0 0 0 0** 0 0 0 0 0 0 * = rstb = 0 or v dd (fail) after v dd = 5.0 v or por ** = except bit d6 (parallel) of the gc r register that is saved when v dd (fail) occurs, provided v dd = 5.0 v and v dd_fail_en = 1 before x = register address, p = parity bit analog integrated circuit device data ? 42 freescale semiconductor 06XS4200 functional device operation logic commands and spi registers
table 12. serial output register bit assignment bits d13, d2, d1, d0 of the previous statr so returned data s o a 3 s o a 2 s o a 1 s o a 0 od 15 od 14 od 13 od 12 od 11 od 10 o d9 od8 od7 od6 od5 od4 od3 od2 od1 od0 statr 0 0 0 0 wdi n pf soa 3 soa 2 so a1 so a0 n m ov uv por r_ful l1 r_ful l0 fault1 fault0 out1 out0 fault r_s a 0 0 0 1 wdi n pf soa 3 soa 2 so a1 so a0 n m otw 0 0 olon _s oloff _s os_s ot_s sc_s oc_s pwmr_ s a 0 0 1 0 wdi n pf soa 3 soa 2 so a1 so a0 n m on_ s pwm 7_ s pwm6 _s pwm5 _s pwm4 _s pwm3_s pwm2_s pwm1_s pwm0_s confr _s a 0 0 1 1 wdi n pf soa 3 soa 2 so a1 so a0 n m os_ dis_s olo n_di s_s oloff _dis_s dir_di s_s sr1_s sr0_s delay2_s delay1_ s delay0_ s ocr_s a 0 1 0 0 wdi n pf soa 3 soa 2 so a1 so a0 n m hoc r_s pr_s clock_i nt_ s csns_ ra tio_s toch_ s tocm_s och_s ocm_s ocl_s retry r_s a 0 1 0 1 wdi n pf soa 3 soa 2 so a1 so a0 n m ofp r3 r2 r1 r0 auto_period 1_s auto_period0 _s retry_unli mite d_s retry_s gcr 0 1 1 0 wdi n pf soa 3 soa 2 so a1 so a0 n m pwm _en_ 1 pwm _en _ 0 paral ll el t_h_e n wd_di s vdd_fail_e n csns1_en csns0_e n ov_dis diagr 0 1 1 1 wdi n pf soa 3 soa 2 so a1 so a0 n m con f1 con f0 id1 id0 in1 in0 clock_fail cal_fail1 cal_fail0 content s af ter reset or failure* n/ a n/ a n/ a n/ a 0 0 0 0 0 0 0 0 0 0** 0*** 0 0 0 0 0 * = rstb = 0 or v dd (fail) after v dd = 5.0 v, or por ** = except bit d6 (parallel) of the gcr register that is saved when v dd (fail) occurs provided v dd = 5.0 v and vdd_fail_en = 1 before *** = except bit d7 (por) of the statr register that is saved when v dd (fail) occurs after v dd = 5.0 v and vdd_fail_en = 1 (fail-safe mode ) x = register address, pf = parity fault analog integrated circuit device data ? freescale semiconductor 43 06XS4200 functional device operation logic commands and spi registers si register addressing the address in the title of the following sections (a 0 xxx) refer to bits d[13:10] of the spi word required to address the associated si register. bit a 0 = d13 selects between registers of bank 0 and bank 1 ( table 13 ). the function assignment of register bits d[8:0 ] is described in the associated section. the ?_s? behind a register name indicates that the variable applies to the register contents of both banks. table 13. value of bit a 0 required for addressing register banks 0 or 1 value a 0 (d13) bank 0 0 = channel 0 (default) 1 1 = channel 1 address a 0 000 ? status register (statr_s) to read back the contents of any of the 13 so registers, bits d[13:10] of the channel?s si statr register must be set to a 0 000 and bits d[2:0] in the same spi word to the address of the desired so register. t he so registers thus addressed are: statr, faultr_s, pwmr_s, confr_s, ocr_s, retry_s, gcr, and diagr ( table 12 ). address a 0 001? pwm control register (p wmr_s ) the pwmr_s register conten ts determines the value of the pwm duty cycle at the output ( table 11 ), both for internal and external clock signals. bit d8 must be set to 1 to acti vate this function. the desired value of duty cycle is obtained by setting bits d7:d0 to one of the 256 levels as shown in table 6 .to start the
analog integrated circuit device data ? 44 freescale semiconductor 06XS4200 functional device operation logic commands and spi registers pwm function at a known point in time, the pwm_en_s bit (both in the gcr register) must be set to 1. address a 0 010? channel configuration regi ster (confr_s ) the confr_s is used to select the appropriate value of slew rate and turn-on delay. the settings of bits d[8:6] determine the activation of open-load and short-circuit (to v pwr ) detection. bit d13 ( = a 0 ) of the incoming spi word determines which of both confr registers is addressed ( table 13 ). setting bit d8 (os_dis_s) to logic [1] disables detection of short-circuits b etween the ch annel?s output pin and the vpwr pin. the default value [0] enables the feature. setting bit d7 (olon_dis_s) to logic [1] disables detection of o pen-load in the on state for the selected channel. the default value [0] enables this feature ( table 14 ). setting bit d6 (oloff_dis_s) to logic [1] disables detection of open-load in the of f state. the default value [0] enables the feature, see table 14. table 14. selection of open-load detection features olon_dis_s (d7: on state) oloff_dis_s (d6: off state) selected open-load detection function 0 0 both enabled (default) 0 1 off state detection disabled 1 0 on state detection disabled 1 1 both disabled setting bit d5 (dir_dis_s) to logic [0] will enable direct control o f the selected channel. setting bit d5 to logic [1) will disable direct control. in t hat case, the channel state is determined by the settings of the internal pwm functions. d4:d3 bits (sr1_s and sr0_s) control the slew rate at tu rn on and turn off ( table 15 ) take place. the default value ([00]) corresponds to the medium slew rate. rising and falling edg e slew rates are identical. table 15. slew rate selection sr1_s (d4) sr0_s (d3) slew rate 0 0 medium (default) 0 1 low 1 0 high 1 1 medium sr analog integrated circuit device data ? freescale semiconductor 45 06XS4200 functional device operation logic commands and spi registers the dc motor profile only has one over-current window defined by only two different thresholds (i _och and i _ocl) as illustrated by figure 6 . in this case, the maximum over- current duration is selected among four values: t ocm1_m , t ocm2_m , t och1 , and t och2 . table 17. dynamic over-current threshold activation times for bulb -and dc motor profiles conf[x] t och_s (d4) t ocm_s (d3) selected threshold activation times 0 0 0 t och1 and t ocm1_l 0 0 1 t och1 and t ocm2_l 0 1 0 t och2 and t ocm1_l 0 1 1 t och2 and t ocm2_l 1 0 0 t ocm1_m 1 0 1 t ocm2_m 1 1 0 t och1 1 1 1 t och2 bit d2 (och_s) selects the value of the higher (upper) over-current threshold among two values. the default value [0] corresponds to the highest value, and [1] to the lowe st value ( table 18). table 18. och upper current threshold selection och_s (d2) i _och current threshold 0 i _och1_s (default) 1 i _och2_s bit d1 (ocm_s) sets the value of the middle over-current th reshold. the default value [0] corresponds to the highest valu e, and [1] to the lowest value ( table 19 ). in dc motor mode, there is no middle over-current threshold and the value of this bit has no influence. table 19. ocm current threshold selection ocm_s (d1) ocm current threshold 0 i _ocm1_s (default) 1 i _ocm2_s bit d0 (ocl_s) and d8 (hocr) set the value of the lowest over-curren t threshold, as shown in table 20 . table 20. ocl current threshold selection hocr (d8) ocl_s (bit d0) selected ocl current level 0 0 i _ocl1_x (default) 0 1 i _ocl1_x 1 0 i _ocl2_x 1 1 i _ocl3_x address a 0 101 ? auto-retry register (r etryr_s) the retryr_s register contents are used to set the different auto-retry options ( auto-retry ) and the offset compensation feature of the current sense function. setting bit d8 to 1(ofp = 1) causes the random offset current to be add ed to the sensed current (pin csns). setting bit d8 to 0 results in the offset current being subtracted from the sensed current. setting d3 and d2 ( table 21 ) to the appropriate values allows selection of the value of the auto-retry period among four predefined values. table 21. auto-retry period auto_period1_s (d3) auto_period0_s (d 2) retry period 0 0 t auto_00 (default) 0 1 t auto_01 1 0 t auto_10 1 1 t auto_11 setting bit d1 to 1 (retry_unlimited_s = 1) results in an un limited number of auto retr ies, provided the auto-retry function wasn?t disabled. setting bit d1 to 0 (retry_unlimited_s = 0) limits the amou nt of auto retries to 16 (see amount of auto-retries ). the value of the counter will neith er b e reset after delatching, nor when the fault disappears. setting bit d0 (retry_s) will enable or disable auto-retry, accord ingly to setting of the conf pin. for conf[x] = 0 (lighting profile configured), setting retry_s = 1 disables auto-retry. the default value [0] enables it. for conf[x] = 1 (dc motor), setting retry_s = 1 enables au to-retry. the default value [0] disables it. address 0110 ? global configuration register (gcr) the gcr register is used to ac tivate various functions and diagnostic functions table 11 . setting bits d8 = 1 and d7 = 1 of the gcr register (pwm_e n_1 and pwm_en_0) will activate the internal pwm
analog integrated circuit device data ? 46 freescale semiconductor 06XS4200 functional device operation logic commands and spi registers function of both channels simultaneously according to the values of duty cycle and turn -on delays in the pwmr_s and confr_s registers ( table 6 ). however, this option should never be used to drive channels in parallel. to increase the loa d current capability, the instructions in the section parallel operation should be followed. setting bit d6 will set parallel mode (improved switching synchron ization between both channels). only configuration and diagnostic information of bank 0 (a 0 = 0) is available in th is setting (see parallel operation ). setting bit d5 (t_h_en = 1) activates track & hold current sensin g mode. when t&h is ac tivated, the value of the channel?s load current is kept available after turn-off. setting bit d4 (wd_dis = 1) disables the spi watchdog fu nction. a logic [0] enables the spi watchdog. setting bit d3 (v dd_fail_en = 1) will enable or disable the v dd failure detection. when enabled, the device will enter fail-safe mode after v dd < v dd(fail). bits d6 (parallel bit), d2 and d1 set the different (current) sensing options. the csns pin outputs a scaled value of the selected channel?s load current, the sum of both currents or the die temperature, according to the values in table 22 . when the highest over-current range is selected (bit d8 of the ocr register, hocr = 0), the device?s csns pin will only outpu t scaled values of a single channel?s load current. table 22. current sense pin functionality selection d8 d6 d2 d1 activated function at csns pin x x 0 0 disabled 0 x 0 1 current sensing on channel 0 0 x 1 0 current sensing on channel 1 0 x 1 1 temperature sensing 1 0 0 1 current sensing on channel 0 1 x 1 0 current sensing on channel 1 1 x 1 1 temperature 1 1 0 1 current sensing summed currents of chann els 0 and 1 setting bit d0 (ov_dis = 1 of the gcr reg.) will disable over-voltag e protection. setting this bit to [0] (default), will enable it. address a 0 111 ? calibration register (c alr_s) the internal clock frequency of both channels can be calibrated independently. settin g the appropriate calibration word in the calr_s register ( table 11 ) puts the device in calibration mode. the default switching frequency is 400 hz, but can be chan ged by applying a specific calibration procedure. see internal clock & intern al pwm (clock_int_s bit = 1) . so register addressing the device has two register banks, each of which has five channel-specific so register s containing the channel?s configuration and diagnostics status ( table 12 ). these registers are faultr_s, pwmr_s, confr_s, ocr_s, and retryr_s. global fault and diagnostic information is contained in the follo wing common so-registers: statr, gcr, and diagr. all the so registers can be addressed by setting the appropriate bits in the si-sta tr_s register (bits d13, d2, d1, d0). the value of the bit d13 determines which register bank is addressed (bank 0 or 1). data is made available the next cycle after register addressing. the output status register corre ctly reflects the contents of the addressed so register as long as csb is low, except when the data from the previous spi cycle was invalid. in this case, the device outputs the cont ents of the last successfully addressed so register. serial output register assignment the output register that will be shifted out through the so pin is previously addressed by bits d13, d2, d1, and d0 of the statr_s si register ( table 11 ). table 12 gives the functional assignment (od15 : od0) of each of the thirteen so regi ster bits, preceded by the address of the si statr_s required to address it. ? bit od15 (msb) reports t he state of the watchdog bit from the previously clocked-in spi message. ? bit od14 (pf, active 1) repo rts an eventual parity error on the previously transferred si register contents. ? bits od13:od10 echo the stat e o f bits d13, d2, d1, and d0 (soa3: soa0) of the previously received si word. ? bit od9: normal mode (nm) reports the device state. in normal mode, nm = 1. ? bits od8 : od0 are the contents of the selected so regi ster (addressed by bit d13 and bits d2 : d0 of the previ ous si statr register). previous address soa 3 : soa 0 = 0000 (statr) when bits soa3?soa0 of the previously received si statr_s register = 0000, the so statr register will be ad dressed. bits od8: od0 contain the relevant channel in formation: faults, channel state, and supply voltage errors. ?bits od8: od6 report failures common to both channels ?bit od8 = ov = 1: over-voltage fault ?bit od7 = uv = 1: under-voltage fault ?bit od6 = por = 1: power-on reset (por) has occurred power-on-reset occurs when v pwr analog integrated circuit device data freescale semiconductor 47 06XS4200 functional device operation logic commands and spi registers bits od3 (fault1) and od2 (fault0) are set to logic [1] when channel-specific (non-gene ric) faults are detected: faults = oc_s + sc_s + ot_s + os_s + oloff_s + olon_s. the faults bit can be reset by reading out the common statr register or the individual faultr_s register (provided the fault has disappeared). bits od1: od0 (out1 and out0) report the channel?s switching state (on/off) in real time. previous address soa 3 : soa 0 = a 0 001 (faultr_s) bit od8 of both fault regi sters (faultr_s) is set simultaneously when the over-temperature prewarning (otw) condition occurs, but t he channels are not switched off (temperature of the common gnd pin (#14)> t otwar ). reading either fault register clears both otw bits. bits od5: od0 of the fault register (faultr_s) report the faults that occurred on the channel previously selected by bit soa3 = a 0 ( table 13 ). ?bit od0 = oc_s: over-current fault on channel s, ?bit od1 = sc_s: severe short-circuit on channel s, ?bit od3 = os_s: output shorted to v pwr on channel s, ?bit od4 = oloff_s: open load in off state on channel s, ?bit od5 = olon_s: open load in on state on channel s. (the threshold value above which this fault is triggered depends on the selected current sense ratio; for csr0 @ 500 ma typ. and for csr1 @ 7.0 ma typ.). the fault status pin ( fs) is set to 0 (active low) upon occurrence of any of the a bove mentioned faults. latched faults can only be delatched by the procedure described in fault delatching . the faultr_s register is reset when it is read out, provided that the failure cause has disappeared and latched faults had been delatched. previous address soa 3 : soa 0 = a 0 010 (pwmr_s) the device outputs the cont ents of the addressed pwmr_s register (a 0 = 0 for bank 0 and a 0 = 1 for bank 1). previous address soa 3 : soa 0 = a 0 011 (confr_s) the device outputs the contents of the addressed confr_s register (a 0 = 0 for bank 0 and a 0 = 1 for bank 1). previous address soa 3 : soa 0 = a 0 100 (ocr_s) the device outputs the content s of the addressed ocr_s register (a 0 = 0 for bank 0 and a 0 = 1 for bank 1). previous address soa 3 : soa 0 = a 0 101 (retryr_s) the device outputs the contents of the addressed retryr_s register (a 0 = 0 for bank 0 and a 0 = 1 for bank 1). bit od8 contains the value of the ofp bit (offset positive), used for current sense offs et compensation. bits od7: od4 contain the real time value of the auto-retry counter. when these bits contain [0000], ei ther auto-retry has not been enabled or auto-retry did not occur. previous address soa 3 : soa 0 = 0110 (gcr) the device outputs the contents of the general configuration register (gcr) common to both channels. previous address soa 3 : soa 0 = 0111 (diagr_s) bit od8 ( ch. 1 = conf1) and bit od7 ( ch. 0 = conf0) of the diagr_s register contai n the values of the channels? configuration bits (0 = bulb, 1 = dc motor) bits od6:od5 contain the pr oduct identification (id) number, equal to 10 for the present dual 6.0 m : product. bits od4:od3 report the logic state of the direct inputs in[1:0] in real time (1 = on, 0 = off), od4 = ch. 1, od3 = ch. 0. bit od2 reports a logic [1] in case an external clock error occurred (if an external clo ck was selected by clock_int = 0) bit od1:od0 report logic [1] in case a calibration failure occurred during calibration of a channel?s internal clock period.
analog integrated circuit device data ? 48 freescale semiconductor 06XS4200 typical applications typical applications figure 21 shows the electrical ci rcuit of a typical truck application. a 70 w lamp and 120 w dc motor are driven. as an example, an external circuit is added that takes over load control in case fail-safe mode is activated (fsob goes low). this circuit allows keeping full control of both channels in case of spi failure. v dd v dd gnd mcu voltage regulator v pwr hs0 hs1 vpwr vdd clock fsb in0 sclk csb si so rstb in1 100 nf i/o i/o sclk csb si so 2.0 k load 0 load 1 csns a/d v dd vdd v pwr v dd 22 nf 22 nf 1.0 k2 external control circuitry vpwr 10 f 100 nf 10 f 100 nf 10 k 10 k fsob 10 k v pwr 100 k m conf1 conf0 direct controls (pedals, handles, etc.) gnd sync a/d i/o 22 nf 10 k 06XS4200 8k2 75 k 100 nf 1.0 f figure 21. typical application with two different load types
analog integrated circuit device data ? freescale semiconductor 49 06XS4200 typical applications . v dd gnd mcu hs0 hs1 vpwr vdd clock fsb in0 sclk csb si so rstb in1 100 nf i/o i/o sclk csb si so load csns a/d v dd v dd v pwr v dd 22 nf 22 nf 2.0 k vpwr 100 nf 10 k fsob 10 k v pwr 100 k m conf1 conf0 direct controls (pedals, handles,...) gnd sync a/d i/o 10 k 06XS4200 1.0 k2 75 k 75 k 1.0 ?f external control circuitry v dd voltage regulator v pwr 10 f 100 nf 10 f 100 nf figure 22. two channels in parallel / recommended external current sense circuit
analog integrated circuit device data ? 50 freescale semiconductor 06XS4200 packaging soldering information packaging soldering information the 06XS4200 is packaged in a surface mount power package (pqfn), intended to be soldered directly on the printed circuit board. the maximum peak temperat ure du ring the soldering process should not exceed 260 c for 10 seconds maximum du ration. the an2467 provides guidelines for printed circuit board design and assembly. marking information the device is identified by the part number: 06XS4200. device markings indicate information on the week and year of manufacturing. the date is coded with the last four characters of the nine character build information code (e.g. ?ctkah0929?). the date is coded as four nu merical digits where the first two digits indicate the year and the last two digits indicate the week. for instance, the date code ?0929? indicates the 29 th week of the year 2009. package mechanical dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number. package suffix package outline drawing number 23-pin pqfn fk 98asa00428d
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? freescale semiconductor 51 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? 52 freescale semiconductor 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? freescale semiconductor 53 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? 54 freescale semiconductor 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? freescale semiconductor 55 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? 56 freescale semiconductor 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? freescale semiconductor 57 06XS4200 packaging package mechanical dimensions
fk suffix 23-pin pqfn 98asa00428d issue b analog integrated circuit device data ? 58 freescale semiconductor 06XS4200 packaging package mechanical dimensions
analog integrated circuit device data ? freescale semiconductor 59 06XS4200 revision history package mechanical dimensions revision history revision date description of changes 1.0 8/2012 ? initial release.
analog integrated circuit device data 60 freescale semiconductor 06XS4200 revision history package mechanical dimensions
document number: mc06XS4200 rev. 1.0 8/2012 information in this document is provi ded solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabric ate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be pr ovided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/p olicy.aspx?selector=rt&s=str0326182960&pc. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c- ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, sm artmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc.

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